Adriaan Sadie

Last seen: 5 years 前 | 自 2018 起处于活动状态

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How do I add FPGA data capture IP core in existing Vivado project?
I am using the FPGA data capture component from Matlab (generateFPGADataCaptureIP) to generate a logic analyzer IP core which I ...

5 years 前 | 2 个回答 | 0

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How can I access future samples of a discrete time signal in Simulink?
Hi I am busy with a project that implements model predictive control and it uses a reference signal's future sample values, i...

6 years 前 | 0 个回答 | 0

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