SerDes Design and Verification for PAM3 and PAM4 High-Speed Digital Links

Welcome to this MathWorks presentation on SerDes Design and verification, with focus on PAM3 and PAM4 high-speed digital links. My name is Giorgia Zucchelli, and I'm the Technical Marketing Manager for MathWorks RF Mixing and product areas. So let's get started.

If you're not familiar with high-speed digital links, this is how a typical SerDes system looks like. It is composed by a transmitter, a channel representing the physical interconnect, and a receiver. The channel introduces imperfections such as noise, dispersion, and crosstalk. And these imperfections need to be corrected by analog and digital equalization algorithms.

Most of the equalization complexity is in the receiver, where the digital signal is recovered after being distorted by the channel. Design of a typical SerDes system is quite complex, and it starts from given specification, or standard requirements. For example, to design a USB ethernet, or a PCI Express link. Based on the specs, the system architecture is chosen.

At this stage, for example, you determine if this system includes pre-emphasis, or if it is based on an ADC, or if it uses global or local optimization. With the next generation systems, the complexity of the design is constantly increasing. For example, most first-generation systems use NRZ modulation. That is to say, a binary or two-level modulation.

With increasing requirements on speed and data rates, most next-generation systems use multi-level, or pulse amplitude modulation, such as PAM3 or PAM4. These make the system more complex to design as the equalization, the clock and data recovery, and the performance metrics need all to be enhanced to deal with multilevel signals.

You might have many different questions when designing and integrating the SerDes System. This webinar will help you with answering many of the questions that you might have, and gain insight in your design. In the next half hour, using code example and executable models, we will describe how to design and verify the next-generation SerDes System.

We will see how to get started, how to use measurement data to improve the fidelity of your SerDes model. We will include channel dispersion, crosstalk, and transmitter and receiver jitter. When elaborating the SerDes system design, we will see how an accurate model of the SerDes transceiver can help to assess the implementation trade-offs, and to determine adaptation algorithms.

For example, we will see how to determine such things as the type of equalization, the number of tops or the strategy of optimization. At last, we will discuss the importance of IBIS-AMI my model generation. If all of this sounds very complicated, don't worry. With SerDes Toolbox, we've made simple things easy and complex things possible.

You can use the SerDes Designer App to get started, even if you know very little about SerDes design. First, you define assistance specifications. The sample rate, type of modulation, the type of signaling if differential or singlehanded. You can then add to your system the building blocks of the service chain. For each block, you can change the properties.

For example, the poles and zeros, or the number of tops. And once you have built your chain, you can analyze it including crosstalk or jitter. And at the end, you can export it as a script or as an executable Simulink or IBIS-AMI model. Let's see the SerDes Designer app in action.

You can launch the SerDes Designer app from the app toolstrip in MATLAB. When you open the app, there is already a placeholder for the channel and the analog drivers. To the left of the channel we have the transmitter, and to the right, the receiver. The channel is described by default with an IEEE behavioral model of a transmission line.

In this case, for example, the model specifies A to B attenuation at five gigahertz. At higher frequencies, the attenuation will be higher. You can also import the impulse response of an arbitrary channel. This allows you to model the channel, for example using guest parameters, either from measurement data, or from electromagnetic simulators. The analog drivers at the input and at the output use typical parameters that you will find in the IBIS-AMI standard.

And they help you to further improving the accuracy of the channel model. When developing a SerDes System, the entire goal is to reduce the imperfections introduced by the channel. So it is extremely important having a realistic model. Before we start with a SerDes design, let's visualize the eye diagram of the received signal.

This is the signal that we would receive with this channel, and without performing any equalization. Before we start with the actual SerDes design, you need to specify the data rate at which the system works by providing the symbol time. In this case, a symbol time of 100 picoseconds corresponds to 10 gigabit per second link.

Second, you need to decide which modulation to use, if NRZ, PAM3, or PAM4. By default, the signal has just two levels. But for example, if you select PAM3, we will use a [? tone ?] signal, and the eye diagram will now show two openings.

Now we can start adding equalizers to our system by selecting components from the Block Gallery. Let's start by adding a pre-emphasis filter. We add a fit forward equalizer, FFE, to our transmitter. The FFE can have any arbitrary number of tops.

The top that has the largest amplitude is the main top. All the tops before it are precursor tops. And ones after it are post-cursor tops. You can visualize the pulse response of the channel. Here you see two curves. The first just represents the channel, and a second at the effect of equalization.

Equalized waveform is delayed by one sample time, as the FFE as one precursor top. To determine a preliminary estimate of the top value, we can add a marker to the curve. What would change the FFE tops, we evaluated the eye diagram. As you can see, the FFE is effective as the eye opens up.

As you noticed, the analysis results were updated almost instantaneously. This is because the app performs a linear time invariant analysis of the SerDes chain. This is equivalent to an init analysis in IBIS-AMI terminology. Although the statistical eye is helpful, you might be looking for a more measurable way to assess results.

For example, you can plot the bit error rate and the bathtub curve, and also visualize the contour plot of the eyes for the given target bit error rate. The alternative, you can just ask the app to provide a report of all the metrics. As you can see, the opening of the two eyes is reported as well as the channel operating margin, or COM.

You can now continue with the design of the receiver equalization. For example, we can add a continuous time linear equalizer, or CTLE. For the CTLE, you can specify a family of characteristics. And you can visualize the CTLE curve to better understand the specifications.

For example, in the default case, we have a family of nine curves, each with a different DC gain and peaking gain specified at five gigahertz of frequency. We can change the specs to DC gain and AC gain, or AC gain and peaking gain. These three ways of specifying the CTLE curve are essentially equivalent, and each describes an analog filter with two poles and one zero.

When the CTLE operates in adapt mode, the curve that provides the minimal MSNR is chosen. The chosen curve is indicated in the report, actually. You can change the mode to be fixed, and we can verify results by selecting a specific CTLE curve. You can also describe the CTLE curves with an arbitrary number of poles and zeros, and use the gain pole zero, or GPZ matrix specification.

In this case, you can specify a matrix where each row represents a curve. The GPZ matrix method allows you to describe an arbitrary filter. For example, fitted on real life measurement or simulation data. In this example, the CTLE transfer function is imported from CSB file.

The first column represents the frequency. The second and third columns represent the real and imaginary part of the CTLE transfer function. Once we import the data, we can just fit it and create an equivalent Laplace transform function using the rational method. In this case, the fitting provides a really good quality with just two poles.

From the rational object, we can extract the DC gain, poles, and zero, and create a GPC matrix to use in the CTLE object. We can verify the fitting by plotting the original data in the fitted results. We did a good job here. Now for example, we can use the measure CTLE curve in our design.

But actually, if you look at the results, they're really not great. So let's better revert to the original configuration. We can now continue our design, and for example, add decision feedback equalizer, or DFE to our receiver. The DFE minimizes the inter-symbol interference, or ISI, at the clock sampling times.

For this reason, the DFE block also includes a CDR, or clock and data recovery system. How this system works is extremely well described in the SerDes documentation with lots of details and examples. This DFE has four tops, which are automatically adapted. The adapted values are given in the report.

You can experiment and for example add one more top, and verify the results in the report. As you can see, results are computed rapidly thanks to the LTI analysis of the system. Before adding more components to the transmitter and receiver, you might want to verify how well the SerDes system operates in presence of jitter.

The app allows you to specify both transmitter and receiver jitter. For transmitter and receiver, you can specify duty cycle distortion, random jitter, RJ, deterministic jitter, DJ, and sinusoidal jitter at a given frequency. You can specify jitter in seconds, or as a fraction on the UI.

You can operate either in clocked mode or in ideal mode. In the first case, the jitter eye is [INAUDIBLE] with a clock probability density function. While in the ideal case, the clock PDF is given seperately. Additionally, you can just add a noise floor to the receiver signal.

Next to jitter in the app, we can also specify one additional impairment, the channel crosstalk. Crosstalk happens when you have multiple adjacent lanes on a PCB, or when you have wires that are coupled with each other. In the app, you can specify crosstalk using a number of predefined options given by the CEI ethernet standard.

Alternatively, you can provide custom crosstalk specifications in terms of far-field and near-field integrated crosstalk noise. With the SerDes Designer app, you can explore different architectures very rapidly and analyze all sorts of what-if scenarios. For example, to change the entire system to operate with PAM4 modulation, you just need to change a single setting.

Additionally you might want to automate the design space exploration. For example, iterating through multiple configurations. For this we can just generate the MATLAB script from the app. This script reproduces step-by-step the system that we designed in the app. If you execute the script, the analysis results are shown as MATLAB figures.

You can customize the script, for example, to loop through a number of configurations. Additionally, you can automatically generate a report such as a PDF document, to share, for example, with your colleagues. Before we continue further, let's summarize what we have seen so far.

With the SerDes Designer app, you can get started with SerDes design even if you're not an expert. You can design and analyze SerDes systems, including transmitters and receivers with arbitrary configuration of equalization algorithms. You can import measurements and component specifications like we did, for example, for the CTLE.

You can perform statistical analysis and visualize the eye diagram, bit error rate, bathtub curve, pulse response, or measure the channel operating margin, COM And you can do all of the above while accounting for jitter and crosstalk. But SerDes Toolbox doesn't stop here.

From the SerDes Designer app, you can export your SerDes design as a Simulink model. This enables advanced design and optimization. First of all in Simulink, you can simulate the model and the time domain. So you can see the effects of adaptation and account for example for non-linearity. This can hardly be done with an LTI model such as the one that we used in the app.

Since the actual models used in Simulink and the app are the same, actually the LTI and the time domain results are absolutely consistent. In Simulink, you can inspect the algorithms implemented by each of the building blocks. All algorithms are white blocks and suitable for customization.

This does not only apply to the actual blocks, but also to the optimization strategy. This is Simulink in action. From the app, we can automatically generate a Simulink model. If you explore the transmitter of the receiver blocks, you will find the same architecture defined in the app. When you run the simulation, you can follow the progress on the eye scope.

At the end of the simulation, linear and time domain results are reported. If you open one of the blocks, you can actually inspect the source code. That is to say, how the algorithm is implemented in MATLAB. If you are an advanced user, you can copy and modify this code. There's no secret behind it.

Alternatively, if you have existing MATLAB code, or Simulink models that you have already developed, you can use the pass-through block as a placeholder in your model, and use this to add your custom algorithm. In this example, we can, for example, apply a simple non-linear operation to the input signal that compresses the outer eyes.

In a similar way, we could have also used the saturation amplifier from the lightbody. In a Simulink model, not only you can change the algorithms of each of the subsystem blocks, but you can also change the optimization strategy, for example, enabling global optimization. The SerDes toolbox provides many examples to cover advanced customization options.

From the documentation, for example, we can find these three examples, and they show how to customize blocks either on the signal, or on the control datapath. These two examples show how to implement the global optimization of the receiver adaptation algorithm either using the LTI, or the time domain response of the system.

And an entire section of the example category is dedicated to standard-compliant SerDes models, including new architecture such as this high speed system operating at more than 100 gigabit per second using a receiver architecture based on a fast ADC NDSB.

And last, from the Simulink model, you can generate standard-compliant dual IBIS-AMI models. These models can be imported in channel simulators, such as SiSoft, QCD/QSI, and other third party tools. In the channel simulator, you can run regression tests for different channel and parameter configurations. Critical cases that fail can be reported back into the SerDes model either manually or automatically if you use SiSoft tools.

This improves the correlation of the IBIS-AMI model and facilitates a quick turnaround of the verification time. Let's go back to our SerDes model just for a second, and inspect the options for IBIS-AMI model generation. From the configuration block where you set the system level parameters, you can launch the SerDes IBIS-AMI Manager.

You can choose to generate models for the transmitter and receiver. By default, dual models are generated but you can decide to generate gateway or init only. All the files necessary for an AMI models are created for you. Also including a reference IBIS file.

Moreover, for each of the subsystems, you can customize the parameters exposed in the AMI API. If you have SiSoft, or Quantum Channel Designer, or Quantum SI, you can simulate the generated IBIS-AMI models. More specifically with a MathWorks add-on SiSoft link, you can automatically import the IBIS-AMI files into SiSoft QCD and QSI as a specific project.

You can run multiple channel simulation, and if you decide to further this debug a specific configuration, you can back annotate the exact test case into the SerDes Toolbox. This means that you will be using exactly the same stimulus, exactly the same channel, and the same parameters settings. This obviously greatly improves automation, and reduces the chances of manual errors.

As a conclusion, I would like to summarize our SerDes Toolbox covers all aspects of SerDes design and verification. From the SerDes Designer app, you can start the design exploration and rapidly iterate through your specifications, including those impairments such as jitter and crosstalk. In Simulink, you can verify the service performance in the time domain, and customize the model to include proprietary algorithms.

At last, you can generate a standard-compliant dual IBIS-AMI models for the SerDes verification and integration into third party channel simulators. Finally, I would like to present a testimonial of how Intel has used SerDes Toolbox to design a 56 gigabit per second SerDes system as shown in this presentation recorded last year at the MATLAB Expo and presented in this paper at DesignCon.

Moreover, you can also find DDR5 models verified by Intel as examples shipping with the SerDes Toolbox. With this, I thank you for your attention, and I invite you to try the SerDes Toolbox in your next design. You have seen how to get started with the SerDes Designer app, how to improve the fidelity of the model by fitting measured data, and how to include the impact of jitter and noise to determine the margin of your design.

At last we have seen also how you can further optimize and customize your design, and even generate dual IBIS-AMI models for channel verification. All the examples that we covered today are actually part of the product examples. So you find them in the SerDes Toolbox. And please, don't hesitate to reach out to MathWorks if you have any questions. Thank you.