Targeting a Lane Detection Design to a Xilinx Zynq Device | Vision Processing for FPGA, Part 4
From the series: Vision Processing for FPGA
Vision processing applications often use System-on-Chip (SoC) devices such as those from Xilinx® and Intel®, which allow computationally-intensive tasks running on the hardware to work closely with innovative applications running in software. Learn how to convert data types to fixed point and generate optimized HDL with AXI bus interfaces using the HDL Coder™ IP Core Generation Workflow. Details include:
- Visualizing and adjusting fixed-point data types
- Using the HDL Workflow Advisor to generate VHDL
- Setting up and using the IP Core Generation Workflow, mapping the inputs to AXI Stream for Video and the outputs to AXI4 Lite interfaces
- Determining the required clock frequency for processing this video input format
- Generating VHDL and analyzing the results
Published: 14 Sep 2017
