comm.HDLCRCDetector

Detect errors in input data using CRC

Description

This HDL-optimized cyclic redundancy code (CRC) detector System object™ computes a checksum on the input data and compares the result against the input checksum. Instead of frame processing, the HDLCRCDetector System object processes streaming data. The object has frame synchronization control signals for both input and output data streams.

To compute and compare checksums:

Create the comm.HDLCRCDetector object and set its properties.
Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?

Creation

Syntax

CRCDet = comm.HDLCRCDetector

CRCDet = comm.HDLCRCDetector(Name,Value)

CRCDet = comm.HDLCRCDetector(poly,Name,Value)

Description

CRCDet = comm.HDLCRCDetector creates an HDL-optimized CRC detector System object, CRCDet, that detects errors in the input data according to a specified generator polynomial.

example

CRCDet = comm.HDLCRCDetector(Name,Value)sets properties using one or more name-value pairs. Enclose each property name in single quotes. For example,

CRCDet = comm.HDLCRCDetector('Polynomial',[1 0 0 0 1 0 0 0 0], ...
'FinalXORValue',[1 1 0 0 0 0 0 0]);

specifies a CRC8 polynomial and an 8-bit value to XOR with the final checksum.

CRCDet = comm.HDLCRCDetector(poly,Name,Value) creates an HDL-optimized CRC detector System object, CRCDet, with the Polynomial property set to poly, and the other specified property names set to the specified values.

Properties

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Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

`Polynomial` — Generator polynomial
`[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]` (default) | binary vector

Generator polynomial, specified as a binary vector, with coefficients in descending order of powers. The vector length must be equal to the degree of the polynomial plus 1.

`InitialState` — Initial conditions of shift register
`0` (default) | binary scalar | binary vector

Initial conditions of the shift register, specified as a binary, double-precision or single-precision scalar or vector. If you specify this property as a vector, the vector length is the degree of the generator polynomial that you specify in the Polynomial property. If you specify this property as a scalar, the object expands the value to a vector of length equal to the degree of the generator polynomial.

`DirectMethod` — Method of calculating checksum
`false` (default) | `true`

Method of calculating checksum, specified as a logical scalar. When this property is true, the object uses the direct algorithm for CRC checksum calculations.

To learn about direct and non-direct algorithms, see Cyclic Redundancy Check Codes.

`ReflectInput` — Input byte order
`false` (default) | `true`

Input byte order, specified as a logical scalar. When this property is true, the object flips the input data on a bytewise basis before it enters the shift register.

`ReflectCRCChecksum` — Checksum byte order
`false` (default) | `true`

Checksum byte order, specified as a logical scalar. When this property is true, the object flips the output CRC checksum around its center.

`FinalXORValue` — Checksum mask
`0` (default) | binary scalar | binary vector

Checksum mask, specified as a binary, double- or single-precision data type scalar or vector. The object XORs the checksum with this value before appending the checksum to the input data. If you specify this property as a vector, the vector length is the degree of the generator polynomial that you specify in the Polynomial property. If you specify this property as a scalar, the object expands the value to a vector of length equal to the degree of the generator polynomial.

Usage

Syntax

[Y,startOut,endOut,validOut,err] = CRCn(X,startIn,endIn,validIn)

Description

[Y,startOut,endOut,validOut,err] = CRCn(X,startIn,endIn,validIn) computes CRC checksums for an input message X based on the control signals and compares the computed checksum with input checksum. If the two checksums are not equal, the output err is set to 1 true).

Input Arguments

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`X` — Input message and appended checksum
binary column vector | scalar integer

Input message and appended checksum, specified as a binary vector or a scalar integer representing several bits. For example, vector input [0,0,0,1,0,0,1,1] is equivalent to uint8 input 19.

If the input is a vector, the data type can be double or logical. If the input is a scalar, the data type can be unsigned integer or unsigned fixed-point with 0 fractional bits (fi([],0,N,0)).

X can be part or all of the message to be checked.

The length of X must be less than or equal to the CRC length, and the CRC length must be divisible by the length of X.

The CRC length is the order of the polynomial that you specify in the Polynomial property.

`startIn` — Start of input message
logical scalar

Start of the input message, specified as a logical scalar.

`endIn` — End of input message
logical scalar

End of the input message, specified as a logical scalar.

`validIn` — Validity of input data
logical scalar

Validity of input data, specified as a logical scalar. When validIn is 1 (true), the object computes the CRC checksum for input X.

Output Arguments

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`Y` — Message with checksum removed
binary column vector | scalar integer

Message with checksum removed, returned as a scalar integer or binary column vector with the same width and data type as input X.

`startOut` — Start of input message
logical scalar

Start of the input message, returned as a logical scalar.

`endOut` — End of input message
logical scalar

End of the input message, returned as a logical scalar.

`validOut` — Validity of input data
logical scalar

Validity of input data, returned as a logical scalar. When validOut is 1 (true), the output data Y is valid.

`err` — Checksum mismatch
logical scalar

Checksum mismatch, returned as a logical scalar. err is 1 (true) when the input checksum does not match the calculated checksum.

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

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Common to All System Objects

`step`	Run System object algorithm
`release`	Release resources and allow changes to System object property values and input characteristics
`reset`	Reset internal states of System object

Examples

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CRC Encode and Decode for HDL

Open Script

Encode and decode a signal using the HDL-optimized CRC generator and detector System objects. This example shows how to include each object in a function for HDL code generation.

Create a 32-bit message to be encoded, in two 16-bit columns.

msg = randi([0 1],16,2);

Run for 12 steps to accommodate the latency of both objects. Assign control signals for all steps. The first two samples are the valid data, and the remainder are processing latency.

numSteps = 12;
startIn = logical([1 0 0 0 0 0 0 0 0 0 0 0]);
endIn   = logical([0 1 0 0 0 0 0 0 0 0 0 0]);
validIn = logical([1 1 0 0 0 0 0 0 0 0 0 0]);

Pass random input to the HDLCRCGenerator System object™ while it is processing the input message. The random data is not encoded because the input valid signal is 0 for steps 3 to 10.

randIn = randi([0, 1],16,numSteps-2);
dataIn = [msg randIn];

Write a function that creates and calls each System object™. You can generate HDL from these functions. The generator and detector objects both have a CRC length of 16 and use the default polynomial.

function [dataOut,startOut,endOut,validOut] = HDLCRC16Gen(dataIn,startIn,endIn,validIn)
%HDLCRC16Gen
% Generates CRC checksum using the comm.HDLCRCGenerator System object(TM)
% dataIn is a binary column vector. 
% startIn, endIn, and validIn are logical scalar values.
% You can generate HDL code from this function.

  persistent crcg16;
  if isempty(crcg16)
    crcg16 = comm.HDLCRCGenerator()
  end    
  [dataOut,startOut,endOut,validOut] = crcg16(dataIn,startIn,endIn,validIn);
end

function [dataOut,startOut,endOut,validOut,err] = HDLCRC16Det(dataIn,startIn,endIn,validIn)
%HDLCRC16Det
% Checks CRC checksum using the comm.HDLCRCDetector System object(TM)
% dataIn is a binary column vector. 
% startIn, endIn, and validIn are logical scalar values.
% You can generate HDL code from this function.

  persistent crcd16;
  if isempty(crcd16)
    crcd16 = comm.HDLCRCDetector()
  end    
  [dataOut,startOut,endOut,validOut,err] = crcd16(dataIn,startIn,endIn,validIn);
end

Call the CRC generator function. The encoded message is the original message plus a 16 bit checksum.

 for i =  1:numSteps
 [dataOutGen(:,i),startOutGen(i),endOutGen(i),validOutGen(i)] = ...
     HDLCRC16Gen(logical(dataIn(:,i)),startIn(i),endIn(i),validIn(i));
 end

crcg16 = 

  comm.HDLCRCGenerator with properties:

            Polynomial: [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]
          InitialState: 0
          DirectMethod: false
          ReflectInput: false
    ReflectCRCChecksum: false
         FinalXORValue: 0

Add noise by flipping a bit in the message.

dataOutNoise = dataOutGen;
dataOutNoise(2,4) = ~dataOutNoise(2,4);

Call the CRC detector function. The output of the detector is the input message with the checksum removed. If the input checksum was not correct, the err flag is set with the last word of the output.

for i = 1:numSteps
[dataOut(:,i),startOut(i),endOut(i),validOut(i),err(i)] = ...
    HDLCRC16Det(logical(dataOutNoise(:,i)),startOutGen(i),endOutGen(i),validOutGen(i));
end

crcd16 = 

  comm.HDLCRCDetector with properties:

            Polynomial: [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]
          InitialState: 0
          DirectMethod: false
          ReflectInput: false
    ReflectCRCChecksum: false
         FinalXORValue: 0

Use the Logic Analyzer to view the input and output signals.

channels = {'validIn','startIn','endIn',...
    {'dataIn','Radix','Hexadecimal'},...
    'validOutGen','startOutGen','endOutGen',...
    {'dataOutGen','Radix','Hexadecimal'},...
    {'dataOutNoise','Radix','Hexadecimal'},...
    'validOut','startOut','endOut','err',...
    {'dataOut','Radix','Hexadecimal'}};
la = dsp.LogicAnalyzer('Name','CRC Encode and Decode','NumInputPorts',length(channels),...
                      'BackgroundColor','Black','DisplayChannelHeight',8);

 for ii = 1:length(channels)
    if iscell(channels{ii})
        % Display data signals as hexadecimal integers
        c = channels{ii};
        modifyDisplayChannel(la,ii,'Name',c{1},c{2},c{3})
        % Convert binary column vector to integer
        cVal = eval(c{1});
        dat2 = uint16(bit2int(cVal,size(cVal,1))');
        chanData{ii} = squeeze(dat2);
    else
        modifyDisplayChannel(la,ii,'Name',channels{ii})
        chanData{ii} = squeeze(eval(channels{ii})');
    end
 end
la(chanData{:})

Algorithms

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Timing Diagram

This waveform shows streaming data and the accompanying control signals for a CRC16 with 8-bit binary vector input. The input frames are contiguous. The output frames include space between them because the detector block removes the checksum word.

This waveform diagram shows continuous input data. Non-continuous data is also supported.

Initial Delay

The HDLCRCDetector System object introduces a latency on the output. You can compute the latency as follows, assuming the input data is continuous:

initialDelay =  3 * (CRCLength/inputDataWidth) + 2

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

This System object supports C/C++ code generation for accelerating MATLAB^® simulations, and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

The software supports double and single data types for simulation, but not for HDL code generation.

To generate HDL code from predefined System objects, see HDL Code Generation from Viterbi Decoder System Object (HDL Coder).

Version History

Introduced in R2012b

comm.HDLCRCDetector

Description

Creation

Syntax

Description

Properties

`Polynomial` — Generator polynomial
`[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]` (default) | binary vector

`InitialState` — Initial conditions of shift register
`0` (default) | binary scalar | binary vector

`DirectMethod` — Method of calculating checksum
`false` (default) | `true`

`ReflectInput` — Input byte order
`false` (default) | `true`

`ReflectCRCChecksum` — Checksum byte order
`false` (default) | `true`

`FinalXORValue` — Checksum mask
`0` (default) | binary scalar | binary vector

Usage

Syntax

Description

Input Arguments

`X` — Input message and appended checksum
binary column vector | scalar integer

`startIn` — Start of input message
logical scalar

`endIn` — End of input message
logical scalar

`validIn` — Validity of input data
logical scalar

Output Arguments

`Y` — Message with checksum removed
binary column vector | scalar integer

`startOut` — Start of input message
logical scalar

`endOut` — End of input message
logical scalar

`validOut` — Validity of input data
logical scalar

`err` — Checksum mismatch
logical scalar

Object Functions

Common to All System Objects

Examples

CRC Encode and Decode for HDL

Algorithms

Timing Diagram

Initial Delay

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Objects

Blocks

comm.HDLCRCDetector

Description

Creation

Syntax

Description

Properties

Polynomial — Generator polynomial [1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1] (default) | binary vector

InitialState — Initial conditions of shift register 0 (default) | binary scalar | binary vector

DirectMethod — Method of calculating checksum false (default) | true

ReflectInput — Input byte order false (default) | true

ReflectCRCChecksum — Checksum byte order false (default) | true

FinalXORValue — Checksum mask 0 (default) | binary scalar | binary vector

Usage

Syntax

Description

Input Arguments

X — Input message and appended checksum binary column vector | scalar integer

startIn — Start of input message logical scalar

endIn — End of input message logical scalar

validIn — Validity of input data logical scalar

Output Arguments

Y — Message with checksum removed binary column vector | scalar integer

startOut — Start of input message logical scalar

endOut — End of input message logical scalar

validOut — Validity of input data logical scalar

err — Checksum mismatch logical scalar

Object Functions

Common to All System Objects

Examples

CRC Encode and Decode for HDL

Algorithms

Timing Diagram

Initial Delay

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Objects

Blocks

`Polynomial` — Generator polynomial
`[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]` (default) | binary vector

`InitialState` — Initial conditions of shift register
`0` (default) | binary scalar | binary vector

`DirectMethod` — Method of calculating checksum
`false` (default) | `true`

`ReflectInput` — Input byte order
`false` (default) | `true`

`ReflectCRCChecksum` — Checksum byte order
`false` (default) | `true`

`FinalXORValue` — Checksum mask
`0` (default) | binary scalar | binary vector

`X` — Input message and appended checksum
binary column vector | scalar integer

`startIn` — Start of input message
logical scalar

`endIn` — End of input message
logical scalar

`validIn` — Validity of input data
logical scalar

`Y` — Message with checksum removed
binary column vector | scalar integer

`startOut` — Start of input message
logical scalar

`endOut` — End of input message
logical scalar

`validOut` — Validity of input data
logical scalar

`err` — Checksum mismatch
logical scalar

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.