Main Content

Top-Down Design of an RF Receiver

This example uses:

Open Script

This example designs an RF receiver for a ZigBee®-like application using a top-down methodology. It verifies the BER of an impairment-free design, then analyzes BER performance after the addition of impairment models. The example uses the RF Budget Analyzer App to rank the elements contributing to the noise and nonlinearity budget.

Design specifications:

  • Data rate = 250 kbps

  • OQPSK modulation with half sine pulse shaping, as specified in IEEE® 802.15.4 for the physical layer of ZigBee

  • Direct sequence spread spectrum with chip rate = 2 Mchips/s

  • Sensitivity specification = -100 dBm

  • Bit Error Rate (BER) specification = 1e-4

  • Analog to digital converter (ADC) with 10 bits and 0 dBm saturation power

To create fully standard-compliant ZigBee waveforms, you can use the Communications Toolbox Library for ZigBee and UWB Add-on.

This example guides you through the following steps:

  • Develop the baseband transmitter model for waveform generation

  • Determine SNR specification to achieve the 1e-4 BER from a link-level idealized baseband model

  • Derive RF subsystem specifications from equivalent-baseband model of RF receiver and ADC

  • Derive direct conversion specifications from circuit envelope model of RF receiver

  • Perform multi-carrier simulation including interfering signals and derive the specifications of the DC offset compensation algorithm

Design and Verify Baseband Transmitter

To evaluate the performance of the RF receiver design, it is necessary and sufficient to use a signal spectrally representative of an 802.15.4 waveform.

The baseband transmitter model creates and illustrates a spectrally representative ZigBee waveform in the spectral and constellation domains. This model and all the subsequent models use callbacks to create MATLAB workspace variables that parameterize the systems.

Determine Receiver SNR Requirement

To design the receiver, first determine the SNR needed to achieve the specified BER less than 1e-4. calculated in the simulation bandwidth of 4 MHz. Run the link-level model to simulate the receiver processing required to achieve the target BER.

Computing the BER accurately requires alignment of the transmit and receive signals. The simulation must compensate for a two-sample delay of the received signal compared to the transmitted signal. Also, to ensure correct chip-to-symbol-to-bit mapping, the simulation must align the chips to frame boundaries at the input to the Chips to Symbol block on a frame boundary. Accounting for the receive signal delay and the frame boundary alignment requires addition of a Delay block set to a 32-2=30 delay on the receiver branch before recovering the received symbols.

The model achieves a 1e-4 BER at an SNR of -2.7 dB, which can be verified by collecting 100 bit errors.

In the link-level model, the AWGN block accounts for the overall channel and RF receiver SNR budget.

Add ADC and Determine Receiver Total Gain and Noise Figure (NF)

This section uses traditional heuristic derivations to determine the high-level specifications of the RF receiver and ADC.

  • B = 4 MHz = simulation bandwidth = simulation sampling frequency

  • kT = 174 dBm/Hz = thermal noise floor power density

  • Sensitivity = -100 dBm = receiver sensitivity

  • SNR = -2.7 dB

  • Noise power in simulation bandwidth = Pn = sensitivity-SNR = -100 dBm - (-2.7 dB) = -97.3 dBm

  • Pn = kT + 10*log10(B) + NF = -97.3 dBm

Solving for the receiver noise figure (NF):

NF = -97.3 dBm + 174 dBm/Hz -10*log10(4e6 Hz) = 10.7 dB

Derive the receiver gain using the ADC specifications and dynamic range.

  • ADC Number of bits = Nbits = 10

  • ADC Saturation power = Psat = 0 dBm (50 Ohm normalization)

  • ADC Sampling frequency = Fadc = 2.6 MHz

  • ADC Dynamic Range = 6 * Nbits + 1.8 = 61.8 dB

  • Noise power in ADC bandwidth = PNadc = Pn + 10log10(Fadc/Fs) = -99.2 dBm

  • Assuming a 0.1 dB contribution to SNR, Quantization noise = PNadc - 16 dB

  • Receiver Gain = (Psat - Dynamic Range) - PNadc + 16 dB = (0 dBm - 61.8 dB) - (-99.2 dBm) + 16 dB = 53.4 dB

Simulating an idealized baseband model of the RF Receiver, verify the preliminary RF receiver specifications (NF = 10.7 dB and receiver gain = 53.4 dB). This can be done by collecting 100 errors.

The spectrum analyzer shows that the received spectrum with the ADC is roughly identical in shape to the spectrum of the previous section, without the ADC.

Refine Architectural Description of RF Receiver

In this section the RF receiver, and its noise figure and gain budget specifications, are modelled by using four discrete subcomponents with these characteristics:

  • SAW Filter: Noise Figure = 2.3 dB, Gain = -3 dB

  • LNA: Noise Figure = 6 dB, Gain = 22 dB

  • Passive Mixer: Noise Figure = 10 dB, Gain = -5 dB

  • VGA: Noise Figure = 14 dB, Gain = 40 dB

The SAW filter performance is derived from a Touchstone file that specifies S-parameters characteristics. You can verify the gain by visualizing the S21 parameter in the X-Y plane at the operating frequency of 2.45 GHz. You can verify the noise figure by visualizing the NF parameter in the X-Y plane at the operating frequency of 2.45 GHz. Typically, an LNA with low noise and high gain follows the SAW filter, which greatly reduces the impact of the noise figure of the components after the LNA. Also, the passive mixer is specified with a high IP2. Similar to the SAW filter, you can verify the mixer gain by visualizing the S21 parameter in the X-Y plane over a user-specified frequency range of [2e9 3e9].

An equivalent baseband model simulates the refined RF receiver.

Run the simulation and verify the RF receiver link budget by using the output port visualization pane. The total noise figure and gain across the four stages has been divided according to the following budget:

  • Component NF (dB) = [2.3, 6, 10, 14]

  • Component noise factor F (linear) = 10^(NF/10) = [1.78 3.98 10.0 25.1]

  • Power gain (dB) = [-3, 22, -5, 40] = 54 dB > 53.4 dB

  • Voltage gain VG (linear) = 10^(Power gain/20) = [0.71 12.59 0.56 100.0]

  • System noise factor Fsys (linear) = $$1 + [F(1) - 1] + {{[F(2) - 1]} \over {VG(1)}} + {{[F(3) - 1]} \over {VG(1) \times VG(2)}} + {{[F(4) - 1]} \over {VG(1) \times VG(2) \times VG(3)}} = 11.8$

  • System noise figure NFsys (dB) = 10*log10(Fsys) = 10.7 dB

The actual noise figure of the chain, taking into account impedance mismatches, can be verified at the output port of the Equivalent Baseband Model of Receiver, and it is equal to 9.42dB.

With this model you can verify that a BER < 1e-4 corresponds to a Chip Error Rate (ChER) around 7%. By computing ChER, you can run the subsequent models for less time and still collect accurate BER statistics.

Use Circuit Envelope to Simulate Additional RF Impairments

The equivalent baseband modeling technique used in the previous section cannot model a true direct conversion receiver. That model used a mixer with an input frequency of 2.45 GHz and an LO frequency of 2.4 GHz, which led to a spectrum analyzer center frequency of 50 MHz. This modeling limitation motivates a change to the circuit envelope method.

Using the circuit envelope modeling approach, continue refining the RF receiver architecture by adding more realistic impairments.

The circuit envelope model of the RF Receiver differs from the equivalent baseband model as it:

  • Replaces the equivalent baseband mixer with a quadrature modulator, consisting of parameterizable I and Q mixers and phase shifter block, and an LO with impairments

  • Uses broadband impedances (50 ohm) to explicitly model the power transfer between blocks

Comparing spectra, power measurements, and ChER to the equivalent baseband model, there are no significant performance differences. However, with the circuit envelope model, you can include even order nonlinearity effects, I/Q imbalance, and specifications of colored noise distributions for each of the components.

You can manually build the circuit envelope model of the RF Receiver by using blocks from the Circuit Envelope library, or it can be automatically generated using the RF Budget Analyzer app.

The RF Budget Analyzer app

  • Uses Friis equations to determine the noise, gain, and nonlinearity budget of an RF chain, also taking into account impedance mismatches

  • Allows you to explore the receiver design space and determine how to break down the specifications across the elements of the chain

  • Helps you determine which element has the largest contribution to the noise and nonlinearity budget

  • Can generate an RF receiver model with which you can perform multi-carrier simulation and further modify.

Type rfBudgetAnalyzer('TopDownRFReceiverDesign.mat') command at the command line to visualize the RF receiver in the RF Budget Analyzer app.

Add Wideband Interference, LO Leakage, and DC Offset Cancellation

This section modifies the circuit envelope model to create this circuit envelope with interferer model. The circuit envelope with interferer model includes a wideband interfering signal and these impairments:

  • LO-RF isolation of 90 dB in the quadrature demodulator

  • OIP2 equal to 55 dBm in the quadrature demodulator

  • WCDMA-like out-of-band blocker of -30 dBm at 2500 MHz

This simulation models a non-standard-compliant interfering signal that has power and spectral distribution characteristics realistic for a WCDMA signal. The simulation of the wideband interfering signal requires a larger simulation bandwidth of 16MHz. Therefore the 1 MHz OQPSK signal is oversampled by 16, and the Circuit Envelope simulation bandwidth is also increased to 16 MHz.

The design requires a DC offset compensation algorithm to achieve the desired ChER due to the DC offset that results from the LO leakage and the nonlinearity in the demodulator caused by the high out-of-band interfering signal power. In this case you include a very selective filter, that introduces a long latency with corresponding computation delay increases in the ChER measurement block.

The spectrum centered at 0 Hz shows the DC offset compensation reducing the DC offset. As you run the model, note that the DC offset is eventually completely removed.

Conclusion

Following a top-down design methodology, RF receiver components specifications were derived. Impairment, interferer, and RF receiver subcomponent models were iteratively refined to increase fidelity and validated at each stage to confirm overall system performance goals were achieved.