getExpectedPaddedInputData
Class: dlhdl.Processor
Namespace: dlhdl
Description
returns the padded input data according to the convolution thread number of the processor
configuration of the deep learning processor expectedpaddedInput = getExpectedPaddedInputData(hProc,unpaddedInput)hProc.
Input Arguments
Deep learning processor, specified as a dlhdl.Processor
object.
Unpadded input data, specified as a numeric array, cell array, or
dlarray object. If the network input to the processor object is a
dlnetwork object, this argument must be a
dlarray object. The dimensions of this argument must match the
network input layer dimensions. For example, if the input layer size is 224-by-224-by-3,
the unpadded input array size must be 224-by-224-by-3.
Output Arguments
Padded input data returned as a numeric array, cell array, or
dlarray object. The method pads the input data to match the format
of the deep learning processor IP core. To learn more about the data padding format, see
External Memory Data Format.
Examples
Retrieve padded input data for a network with an input layer of size 10-by-10-by-5. The convolution thread number is nine and the expected padded input data should be an array of size 10-by-10-by-8.
Create a network with an input layer of size 10-by-10-by-5.
layers = [imageInputLayer([10,10,5],'Normalization','none') convolution2dLayer(3,3) regressionLayer]; layers(2).Weights = ones(3,3,5,3); layers(2).Bias = ones(1,1,3); net = assembleNetwork(layers);
Create a processor configuration object and set the convolution thread number as nine.
hPC = dlhdl.ProcessorConfig; hPC.setModuleProperty('conv','ConvThreadNumber',9);
hPC =
Processing Module "conv"
ModuleGeneration: 'on'
LRNBlockGeneration: 'off'
SegmentationBlockGeneration: 'on'
ConvThreadNumber: 9
InputMemorySize: [227 227 3]
OutputMemorySize: [227 227 3]
FeatureSizeLimit: 2048
Processing Module "fc"
ModuleGeneration: 'on'
SoftmaxBlockGeneration: 'off'
FCThreadNumber: 4
InputMemorySize: 25088
OutputMemorySize: 4096
Processing Module "custom"
ModuleGeneration: 'on'
Sigmoid: 'off'
TanhLayer: 'off'
Addition: 'on'
MishLayer: 'off'
Multiplication: 'on'
Resize2D: 'off'
SwishLayer: 'off'
InputMemorySize: 40
OutputMemorySize: 120
Processor Top Level Properties
RunTimeControl: 'register'
RunTimeStatus: 'register'
InputStreamControl: 'register'
OutputStreamControl: 'register'
SetupControl: 'register'
ProcessorDataType: 'single'
System Level Properties
TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
TargetFrequency: 200
SynthesisTool: 'Xilinx Vivado'
ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
SynthesisToolChipFamily: 'Zynq UltraScale+'
SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
SynthesisToolPackageName: ''
SynthesisToolSpeedValue: ''Create a processor object and a random input array of size 10-by-10-by-5.
hProc = dlhdl.Processor(Network=net,ProcessorConfig=hPC); im = rand(10,10,5);
Retrieve the padded input data by using the
getExpectedPaddedInputData method. The size of the
output matrix is 10-by-10-by-8.
output = getExpectedPaddedInputData(hProc,im)
Version History
Introduced in R2023b
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