System Integration of Deep Learning Processor IP Core

Generate the deep learning (DL) processor IP core by using HDL Coder™ and Deep Learning HDL Toolbox™. Integrate the generated deep learning (DL) processor IP core into your system design manually or by using HDL Coder and IP core generation workflow

You can integrate the deep learning processor IP core into your system by:

Generating and integrating DL Processor IP Core—Generate a generic deep learning processor IP core by using Deep Learning HDL Toolbox. The generated deep learning processor IP core is a generic HDL Coder IP core with standard AXI4 interfaces. You can integrate the generated generic DL IP core into your Vivado^® or Quartus^® design.
Accelerate the integration of the generated DL processor IP core into your system design by:
- Reading the AXI4 register maps in the generated IP core report. The AXI4 registers allow MATLAB^® or other AXI4 Master devices to control and program the DL processor IP core.
- Using the compiler generated external memory buffer allocation.
- Formatting the input and output external memory data.
Reference design based DL Processor IP core integration—Generate a generic deep learning processor IP core by using Deep Learning HDL Toolbox. Integrate the generated deep learning processor IP core into your custom reference design by using HDL Coder. See Create a Custom Hardware Platform (HDL Coder). You can design the pre-processing and post processing DUT logic in Simulink^® or MATLAB, and use the HDL Coder IP core generation workflow to integrate the pre-processing and post-processing logic with the deep learning processor.
Use MATLAB to run your custom deep learning network on the deep learning processor IP core and retrieve the deep learning network prediction results from you integrated system design.

Functions

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Generate and Integrate DL Processor IP Core

`dlhdl.Workflow`	Configure deployment workflow for deep learning neural network
`compile`	Compile workflow object
`deploy`	Deploy the specified neural network to the target FPGA board
`predict`	Predict responses by using deployed network

Reference Design Based DL Processor IP Core Integration

`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design
`registerDeepLearningMemoryAddressSpace`	Add memory address space to reference design
`registerDeepLearningTargetInterface`	Add and register a target interface
`validateReferenceDesignForDeepLearning`	Checks property values in reference design object

Topics

Generate and Integrate DL Processor IP Core

Generate Custom Generic Deep Learning Processor IP Core
This example shows how to generate a custom generic deep learning processor IP core.
Deep Learning Processor IP Core
Learn about the generated deep learning processor IP core.
Use the Compiler Output for System Integration
Use the compiler outputs to integrate the generated deep learning processor IP core into you design.
External Memory Data Format
Define the input and output external memory data format.
Deep Learning Processor IP Core Report
Learn about the generated files, register address mapping, and how to integrate the generated deep learning processor IP core.
Interface with the Deep Learning Processor IP Core
Choose between batch processing mode and streaming mode to process multiple data frames.
Initialize Deployed Deep Learning Processor Without Using a MATLAB Connection
Deploy your network and deep learning processor IP core to a custom file. Use a script to parse the created file and initialize your deployed network and deep learning processor IP core.

Reference Design Based DL Processor IP Core Integration

Deep Learning Processor IP Core Generation for Custom Board
This example shows how to create custom board and generate a deep learning processor IP core for the custom board.

Featured Examples

Authoring a Reference Design for Live Camera Integration with Deep Learning Processor IP Core

Create an HDL Coder™ reference design that contains a generated deep learning processor IP core. The reference design receives a live camera input and uses a deployed series network to classify the objects in the camera input. This figure is a high-level architectural diagram that shows the reference design that will be implemented on the Xilinx™ Zynq™ Ultrascale+(TM) MPsoC ZCU102 Evaluation Kit.

Open Script

Run a Deep Learning Network on FPGA with Live Camera Input

Model preprocessing logic that receives a live camera input. You implement it on a Zynq® Ultrascale+™ MPSoC ZCU102 board by using a custom video reference design that has an integrated deep learning processor IP core for object classification. This example uses the HDL Coder™ HW/SW co-design workflow. For this example, you need: Deep Learning HDL Toolbox™

Open Script

Deploy and Verify YOLO v2 Vehicle Detector on FPGA

Deploy a you only look once (YOLO) v2 vehicle detector on FPGA and verify the end-to-end application using MATLAB.

Open Script

Deploy Simple Adder Network by using MATLAB Deployment Script and Deployment Instructions File

Create a .dln file for deploying a pretrained adder network. Deploy and initialize the generated deep learning processor IP core and adder network by using a MATLAB® deployment utility script to parse the generated .dln file.

Open Live Script