getUnpaddedOutputData

R2026b

Class: dlhdl.Processor
Namespace: dlhdl

Remove padding from deep learning processor IP core output data

Since R2023b

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Syntax

unpaddedOutput = getUnpaddedOutputData(hProc,paddedData,numofFrames,activationLayer)

Description

unpaddedOutput = getUnpaddedOutputData(hProc,paddedData,numofFrames,activationLayer) returns the unpadded output data for the padded data, paddedData, for the specified number of frames numofFrames, and activation layer of the network in the deep learning processor hProc.

example

Input Arguments

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Deep learning processor, specified as a dlhdl.Processor object.

Padded output data of the deep learning processor IP core, specified as a numeric m-by-1 column vector. The padded output contains padded zeros depending upon the convolution thread number value.

Number of frames of data, specified as a scalar integer. The number of frames is typically the same value as the last dimension of the padded output data.

Activation layer, specified as a character vector. The layer name must correspond to the layer for which the padded output data is retrieved from the deep learning processor IP core.

Output Arguments

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Output data with padding removed, returned as a numeric array. The size of the output data corresponds to the size of the output of the layer specified by activationLayer.

Examples

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Retrieve the padded input data for a network with an input layer of size 10-by-10-by-5. The convolution thread number is nine and the expected padded input data should be an array of size 10-by-10-by-8.

Create a network with an input layer of size 10-by-10-by-5.

layers = [imageInputLayer([10,10,5],'Normalization','none')
convolution2dLayer(3,5,'Padding','same')
regressionLayer];
layers(2).Weights = ones(3,3,5,5);
layers(2).Bias = ones(1,1,5);
net = assembleNetwork(layers);

Create a processor configuration object and set the convolution thread number as nine.

hPC = dlhdl.ProcessorConfig;
hPC.setModuleProperty('conv','ConvThreadNumber',9);
hPC = 

                    Processing Module "conv"
                            ModuleGeneration: 'on'
                          LRNBlockGeneration: 'off'
                 SegmentationBlockGeneration: 'on'
                            ConvThreadNumber: 9
                             InputMemorySize: [227 227 3]
                            OutputMemorySize: [227 227 3]
                            FeatureSizeLimit: 2048

                      Processing Module "fc"
                            ModuleGeneration: 'on'
                      SoftmaxBlockGeneration: 'off'
                              FCThreadNumber: 4
                             InputMemorySize: 25088
                            OutputMemorySize: 4096

                  Processing Module "custom"
                            ModuleGeneration: 'on'
                                     Sigmoid: 'off'
                                   TanhLayer: 'off'
                                    Addition: 'on'
                                   MishLayer: 'off'
                              Multiplication: 'on'
                                    Resize2D: 'off'
                                  SwishLayer: 'off'
                             InputMemorySize: 40
                            OutputMemorySize: 120

              Processor Top Level Properties
                              RunTimeControl: 'register'
                               RunTimeStatus: 'register'
                          InputStreamControl: 'register'
                         OutputStreamControl: 'register'
                                SetupControl: 'register'
                           ProcessorDataType: 'single'

                     System Level Properties
                              TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit'
                             TargetFrequency: 200
                               SynthesisTool: 'Xilinx Vivado'
                             ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-AXIM'
                     SynthesisToolChipFamily: 'Zynq UltraScale+'
                     SynthesisToolDeviceName: 'xczu9eg-ffvb1156-2-e'
                    SynthesisToolPackageName: ''
                     SynthesisToolSpeedValue: ''

Create a processor object and a random input array of size 10-by-10-by-5.

hProc = dlhdl.Processor(Network=net,ProcessorConfig=hPC);
im = rand(10,10,5);

Retrieve the padded input data by using the getExpectedPaddedInputData method. The size of the output matrix is 10-by-10-by-8. Reshape output to an 800-by-1 matrix.

output = getExpectedPaddedInputData(hProc,im);
paddedData = dnnfpga.format.convert3DInputToDDRVectorFormatConv4(output, 4);

Retrieve the unpadded output data by using getUnpaddedOutputData. The size of the unpadded output data corresponds to the size of the conv layer, which is 10-by-10-by-5.

outH = getUnpaddedOutputData(hProc,paddedData',1,'conv');

Version History

Introduced in R2023b

See Also

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