DC Blocker

Block DC component

Libraries:
DSP System Toolbox / Signal Operations
Communications Toolbox / Comm Filters
Communications Toolbox / RF Impairments Correction
DSP System Toolbox HDL Support / Signal Operations

Description

The DC Blocker block removes the DC component of the input signal.

This block supports C/C++ code generation and SIMD code generation. For details, see Code Generation.

Examples

Use DC Blocker to Remove DC Component of Signal

Remove DC component of signal using IIR and Subtract mean estimation algorithms.

Open Model

DC Blocker with Fixed Point Data

Use DC Blocker block to remove DC offset from fixed-point data.

Open Live Script

Ports

Input

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Input — Input signal
scalar | vector | matrix

Specify the input signal that contains the DC component as a scalar, vector, or a matrix.

If the input is fixed point, it must be a signed integer or a signed fixed point value with a power-of-two slope and zero bias.

Data Types: single | double | int8 | int16 | int32 | fixed point
Complex Number Support: Yes

Output

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Output — Output signal with no DC component
scalar | vector | matrix

Output signal with the DC component removed. When the output is fixed-point, it is signed only.

The size, data type, and complexity of the output signal are the same as that of the input signal.

Data Types: single | double | int8 | int16 | int32 | fixed point
Complex Number Support: Yes

Parameters

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Algorithm for estimating DC offset — Algorithm for estimating DC offset
`IIR` (default) | `FIR` | `CIC` | `Subtract mean`

Specify the algorithm used for estimating the DC offset. Select from the following:

IIR uses a recursive estimate based on a narrow, lowpass elliptic filter. This algorithm typically uses less memory than FIR and is more efficient.
FIR uses a nonrecursive, moving-average estimate. This algorithm typically uses more memory than IIR and is less efficient.
CIC uses a lowpass filter that does not employ any multipliers. If the algorithm is CIC, then fixed-point data must be input to the DC Blocker.
Subtract mean computes the means of the columns of the input matrix and subtracts the means from the input. This method does not retain state between inputs. For example, if the input is [1 2 3 4; 3 4 5 6], then the DC Blocker block in Subtract mean mode outputs [-1 -1 -1 -1; 1 1 1 1].

Normalized bandwidth of lowpass IIR or CIC filter — Normalized bandwidth
`0.001` (default) | real scalar in the range (0 1)

Specify the normalized filter bandwidth as a real scalar greater than 0 and less than 1.

Dependencies

The DC Blocker uses this parameter only when the estimation algorithm is set to IIR or CIC.

Order of lowpass IIR elliptic filter — Order of lowpass IIR elliptic filter
`6` (default) | integer greater than 3

Specify the filter order of the lowpass IIR elliptic filter as an integer greater than 3.

Dependencies

The DC Blocker uses this parameter only when the estimation algorithm is set to IIR.

Number of past input samples for FIR algorithm — Number of past input samples for FIR algorithm
`50` (default) | positive integer

Specify, as a positive integer, the number of samples to use when the estimation algorithm is set to FIR.

Dependencies

The DC Blocker uses this parameter only when the estimation algorithm is set to FIR.

Data Types: single | double

View Filter Response — Visualize frequency response
button

Opens the fvtool and displays the magnitude response of the DC Blocker. The response is based on the block parameters. Changes made to these parameters update fvtool.

To update the magnitude response while fvtool is running, modify the block parameters and click Apply.

Simulate using — Type of simulation to run
`Interpreted execution` (default) | `Code generation`

Specify the type of simulation to run. You can set this parameter to:

Interpreted execution –– Simulate model using the MATLAB^® interpreter. This option shortens startup time.
Code generation –– Simulate model using generated C code. The first time you run a simulation, Simulink^® generates C code for the block. The C code is reused for subsequent simulations as long as the model does not change. This option requires additional startup time but provides faster subsequent simulations.

Block Characteristics

Data Types	`double` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`yes^a`
Zero-Crossing Detection	`no`
^a Excludes CIC algorithm for estimating DC offset.

Algorithms

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The DC blocker subtracts the DC component from the input signal. You can estimate the DC component by using the IIR, FIR, CIC, or subtract mean algorithm.

IIR

Pass the input signal through an IIR lowpass elliptical filter.

The elliptical IIR filter has a passband ripple of 0.1 dB and a stopband attenuation of 60 dB. You specify the normalized bandwidth and the filter order.

FIR

Pass the input signal through an FIR filter that uses a nonrecursive moving average from a finite number of past input samples.

The FIR filter coefficients are given as ones(1,Length)/Length, where Length is the number of past input samples for FIR algorithm. The FIR filter structure is a direct form I transposed structure.

CIC

Pass the input signal through a CIC filter. Because the CIC filter amplifies the signal, the filter gain is estimated and subtracted from the DC estimate.

The Cascaded Integrator-Comb (CIC) filter consists of two integrator-comb pairs. These pairs help to ensure that the peak of the first sidelobe of the filter response is attenuated by at least 25 dB relative to the peak of the main lobe. The normalized 3 dB bandwidth is used to calculate the differential delay. The delay is used to determine the gain of the CIC filter. The inverse of the filter gain is used as a multiplier, which is applied to the output of the CIC filter. This ensures that the aggregate gain of the DC estimate is 0 dB.

The following equation characterizes the aggregate magnitude response of the filter and the multiplier:

$| H (e^{j ω}) | = {| \frac{\sin (M \frac{π}{2} B_{n o r m})}{M \sin (\frac{π}{2} B_{n o r m})} |}^{N}$

B_norm is the normalized bandwidth such that 0 < B_norm < 1.
M is the differential delay in samples.
N is the number of sections, equal to 2.

Set the differential delay, M, to the smallest integer such that |H(e^jω)| < 1/√2. Once M is known, the gain of the CIC filter is calculated as M^N. Therefore, to precisely compensate for the filter gain, the multiplier is set to (1/M)^N.

Subtract mean

Compute the mean value of each column of the input signal and subtract the mean from the input. For example, if the input is [1 2 3 4; 3 4 5 6], then a DC Blocker set to this mode outputs [-1 -1 -1 -1; 1 1 1 1].

References

[1] Nezami, M.K. “Performance Assessment of Baseband Algorithms for Direct Conversion Tactical Software Defined Receivers: I/Q Imbalance Correction, Image Rejection, DC Removal, and Channelization.” In MILCOM 2002. Proceedings, 369–76. Anaheim, CA, USA: IEEE, 2002.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

The DC Blocker block supports SIMD code generation using Intel AVX2 code replacement library when the input signal has a data type of single or double.

The SIMD technology significantly improves the performance of the generated code. For more information, see SIMD Code Generation. To generate SIMD code from this block, see Use Intel AVX2 Code Replacement Library to Generate SIMD Code from Simulink Blocks.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Note

For a DC Blocker optimized for HDL code generation, see High Performance DC Blocker for FPGA (DSP HDL Toolbox). The DSP HDL Toolbox™ block provides an HDL-optimized algorithm with hardware-friendly control signals and simulates the latency of the HDL algorithm in Simulink.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Version History

Introduced in R2014a

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R2024a: Change in the default value of Simulate using parameter

The default value of the Simulate using parameter is now Interpreted execution. With this change, the block uses the MATLAB interpreter for simulation by default.

DC Blocker

Description

Examples