Inherit Complexity

Change complexity of input to match reference signal

Libraries:
DSP System Toolbox / Signal Management / Signal Attributes

Description

The Inherit Complexity block copies data at the Data input port with the complexity of the reference signal at the Ref port. When the data input is real and the reference input is complex, the block appends a zero-valued imaginary component, 0i, to each element of the data at the Data input port.

When the data input is complex and the reference input is real, the block outputs the real component of the data input.

When both the data input and reference input are real or when both the data input and reference input are complex, the block propagates the data input with no changes.

Ports

Input

expand all

Data — Data input
scalar | vector | N-D array

Specify the data input as a scalar, vector, or an N-D array.

Ref — Reference input
scalar | vector | N-D array

Specify the reference input as a scalar, vector, or an N-D array.

Output

expand all

Output — Output
scalar | vector | N-D array

Output of the Inherit Complexity block, returned as a scalar, vector, or an N-D array.

Block Characteristics

Data Types	`Boolean` \| `double` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on the memcpy or memset function (string.h) under certain conditions.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

The Inherit Complexity block supports HDL code generation for these input types:

Input complexities, such as real or complex, at the data and reference port
Vector, matrix, and bus inputs

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Limitations

The block has these HDL code generation limitations:

Half-precision data type is not supported.
Non-virtual bus input is not supported.

Version History

Introduced before R2006a

Inherit Complexity

Description

Ports

Input

Data — Data input scalar | vector | N-D array

Ref — Reference input scalar | vector | N-D array

Output

Output — Output scalar | vector | N-D array