Complex Divide HDL Optimized

Examples

Implement Hardware-Efficient Complex Divide HDL Optimized

How to use the Complex Divide HDL Optimized block.

Open Live Script

Customize Output Value of Real Divide HDL Optimized Block When Denominator Is Zero

Use the divideByZero port to customize the value of the block output when division by zero occurs.

Open Live Script

Ports

Input

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num — Numerator
scalar | vector | matrix

Numerator, specified as a scalar, vector, or matrix. num and den must have the same dimensions.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point
Complex Number Support: Yes

den — Denominator
scalar | vector | matrix

Denominator, specified as a scalar, vector, or matrix. num and den must have the same dimensions.

Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point
Complex Number Support: Yes

validIn — Whether input is valid
`Boolean` scalar

Whether input is valid, specified as a Boolean scalar. This control signal indicates when the data from the num and den input ports are valid. When this value is 1 (true), the block captures the values at the input ports num and den. When this value is 0 (false), the block ignores the input samples.

Data Types: Boolean

Output

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y — Output computed by dividing inputs
complex scalar

Output computed by dividing num by den, such that y = num/den, returned as a complex scalar.

Tips

The data type at the output port y is specified by the Output datatype parameter.

Data Types: single | double | fixed point

divideByZero — Whether the value at output is the result of division by zero
`Boolean` scalar

Since R2024b

Whether the value at the y output port is the result of a division by zero operation, returned as a Boolean scalar. When the value of this signal is 1 (true), the corresponding output value at the y port is the result of division by zero. When the value of this signal is 0 (false), the corresponding output value at the y port is the result of division by a nonzero value.

See Division by Zero Behavior for a description of the default divide by zero behavior.

Dependencies

To enable this port, select the Show divide by zero port parameter.

Data Types: Boolean

validOut — Whether output data is valid
`Boolean` scalar

Whether the output data is valid, returned as a Boolean scalar. When the value of this control signal is 1 (true), the block has successfully computed the output at port y. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

Parameters

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Output datatype — Data type of output
`fixdt(1,18,10)` (default) | `single` | `double` | `fixdt(1,16,0)` | `<data type expression>`

Data type of output y, specified as fixdt(1,18,10), single, double, fixdt(1,16,0), or as a user-specified data type expression. The type can be specified directly or expressed as a data type object, such as Simulink.NumericType.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	`OutputType`
Values:	`fixdt(1,18,10)` (default) \| `single` \| `double` \| `fixdt(1,16,0)` \| `<data type expression>`
Data Types:	`char` \| `string`

Example: set_param(gcb,"OutputType","fixdt(1,16,0)")

Show divide by zero port — Whether to show the `divideByZero` port
`off` (default) | `on`

Since R2024b

Select this parameter to show the divideByZero port.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	`dbzPort`
Values:	`0` (false) (default) \| `1` (true)
Data Types:	`logical`

Example: set_param(gcb,"dbzPort",1)

Automatically select CORDIC maximum shift value based on input word length — Automatically select CORDIC maximum shift value based on input word length
`on` (default) | `off`

Since R2024b

Automatically select the CORDIC maximum shift value based on input word length. When this parameter is selected, the default CORDIC maximumShiftValue is equal to wl - 1, where wl = max(num.WordLength + ~issigned(num), den.WordLength + ~issigned(den)).

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	`autoMaximumShiftVal`
Values:	`on` (default) \| `off`
Data Types:	`char` \| `string`

Example: set_param(gcb,"autoMaximumShiftVal","off")

CORDIC maximum shift value — Maximum shift value of hyperbolic vectoring CORDIC
`wl - 1` (default) | `10` | positive integer-valued scalar

Since R2024b

Maximum shift value of hyperbolic vectoring CORDIC, specified as a positive integer-valued scalar. The default value for this parameter is wl - 1, where wl = max(num.WordLength + ~issigned(num), den.WordLength + ~issigned(den)).

Dependencies

To enable this parameter, clear the Automatically select CORDIC maximum shift value based on input word length parameter.

Tips

See Customizable Pipelining for more information.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	`maximumShiftValue`
Values:	`10` (default) \| positive integer-valued scalar
Data Types:	`char` \| `string`

Example: set_param(gcb,"maximumShiftValue","10")

Number of iterations per pipeline register — Number of CORDIC iterations to perform per pipeline stage
`1` (default) | positive integer-valued scalar

Since R2024b

Number of CORDIC iterations to perform per pipeline stage, specified as a positive integer-valued scalar.

See Customizable Pipelining for more information. See How to Interface with the Complex Divide HDL Optimized Block and Hardware Resource Utilization for more information and examples showing how this parameter impacts latency and hardware resource utilization.

Programmatic Use

To set the block parameter value programmatically, use the set_param function.

To get the block parameter value programmatically, use the get_param function.

Parameter:	`nIterPerReg`
Values:	`1` (default) \| positive integer-valued scalar
Data Types:	`char` \| `string`

Example: set_param(gcb,"nIterPerReg","2")

Tips

The blocks Divide by Constant HDL Optimized, Real Divide HDL Optimized, and Complex Divide HDL Optimized all perform the division operation and generate optimized HDL code.

Real Divide HDL Optimized and Complex Divide HDL Optimized are based on a CORIDC algorithm. These blocks accept a wide variety of inputs, but will result in greater latency.
Divide by Constant HDL Optimized accepts only real inputs and a constant divisor. Use of this block consumes DSP slices, but will complete the division operation in fewer cycles and at a higher clock rate.

Algorithms

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CORDIC

CORDIC is an acronym for COordinate Rotation DIgital Computer. The Givens rotation-based CORDIC algorithm is one of the most hardware-efficient algorithms available because it requires only iterative shift-add operations (see More About). The CORDIC algorithm eliminates the need for explicit multipliers.

Division by Zero Behavior

For fixed-point inputs when the denominator den is zero:

If num >= 0, then the output y is equal to upperbound(OutputType).
If num < 0, then the output y is equal to lowerbound(OutputType).

For floating-point inputs, the Complex Divide HDL Optimized block follows IEEE^® Standard 754.

Tip

Enable the divideByZero port to output a flag when the block is given zero as an input value for the divisor.

How to Interface with the Complex Divide HDL Optimized Block

Because of its fully pipelined nature, the Complex Divide HDL Optimized block is able to accept input data on any cycle, including consecutive cycles. To send input data to the block, the validIn signal must be set to true. When the block has finished the computation and is ready to send the output, it will set validOut to true for one clock cycle. For inputs sent on consecutive cycles, validOut will also be set to true on consecutive cycles. Both the numerator and the denominator must be sent together on the same cycle.

The latency depends on the input data type, as summarized in the table. When the input is a fixed-point or scaled double fi, the word length of the inputs num and den can differ. In the table, u represents the input with the larger word length.

Input Type Latency

Input Type	Latency
Fixed point or scaled double `fi`	`ceil((wl + nextpow2(wl) + maximumShiftValue)/nIterPerReg) + 1` where `wl = max(num.WordLength + ~issigned(num), den.WordLength + ~issigned(den))` and `maximumShiftValue = wl - 1` or user-specified value.
Floating point	`0`

Fixed point or scaled double fi

ceil((wl + nextpow2(wl) + maximumShiftValue)/nIterPerReg) + 1

where

wl = max(num.WordLength + ~issigned(num), den.WordLength + ~issigned(den))

and maximumShiftValue = wl - 1 or user-specified value.

Floating point

0

Customizable Pipelining

The Complex Divide HDL Optimized block uses fully pipelined architecture that implements iterative CORDIC-based rotation, normalization, and a CORDIC-based division algorithm. If the inputs num and den are fixed-point or scaled double data types, the block uses multiple pipeline stages for computation. If both inputs are signed and have the same word length, then rotating the denominator into a real value requires num.WordLength iterations. The normalization requires nextpow2(num.WordLength) iterations. The number of CORDIC division iterations depends on the value of the CORDIC maximum shift value parameter. A larger word length can provide higher resolution, but requires more iterations to process. The Complex Divide HDL Optimized block can perform multiple iterations per pipeline stage, which results in lower latency at the cost of a longer critical path in the generated HDL code.

For example, if num and den are signed and have 18-bit word lengths, then rotating the denominator into a real value requires 18 iterations and normalization requires 5 iterations. If the Automatically select CORDIC maximum shift value based on input word length parameter is selected, the CORDIC maximum shift value is 18 - 1 = 17 and requires 17 iterations. The total number of iterations is 18 + 5 + 17 = 40 and the latency of the block is ceil((total number of iterations)/nIterPerReg) + 1. If the number of iterations per pipeline register is set to 1, then the block latency is 41; if the number of iterations per pipeline register is set to 2, then the block latency is 21. If the number of iterations per pipeline register is greater than the total number of required iterations, the block performs all iterations in one pipeline stage and the total latency is minimized to 2.

Hardware Resource Utilization

This block supports HDL code generation using the Simulink^® HDL Workflow Advisor. For an example, see HDL Code Generation and FPGA Synthesis from Simulink Model (HDL Coder) and Implement Digital Downconverter for FPGA (DSP HDL Toolbox).

This example data was generated by synthesizing the block on a Xilinx^® Zynq^®-7000 xc7z045 SoC. The synthesis tool was Vivado^® v2023.1.2.

The following synthesis results show the effect of the Number of iterations per pipeline register parameter on the latency and hardware resource utilization.

nIterPerReg = 1

These parameters were used for synthesis:

Input data type: sfix18_en10
Output data type: sfix18_en10
Input dimension: scalar
Automatically select CORDIC maximum shift value based on input word length: on
Number of iterations per pipeline register: 1
Target frequency: 300 MHz
Latency for this configuration: 41

Resource	Usage	Available	Utilization (%)
Slice LUTs	3246	218600	1.48
Slice Registers	2668	437200	0.61
DSPs	0	900	0.00
Block RAM Tile	0	545	0.00
URAM	0	0

	Value
Requirement	3.3333 ns (300 MHz)
Data Path Delay	2.829 ns
Slack	0.485 ns
Clock Frequency	351.08 MHz

nIterPerReg = 2

These parameters were used for synthesis:

Input data type: sfix18_en10
Output data type: sfix18_en10
Input dimension: scalar
Automatically select CORDIC maximum shift value based on input word length: on
Number of iterations per pipeline register: 2
Target frequency: 150 MHz
Latency for this configuration: 21

Resource	Usage	Available	Utilization (%)
Slice LUTs	2999	218600	1.37
Slice Registers	1393	437200	0.32
DSPs	0	900	0.00
Block RAM Tile	0	545	0.00
URAM	0	0

	Value
Requirement	6.6667 ns (150 MHz)
Data Path Delay	3.153 ns
Slack	3.495 ns
Clock Frequency	315.29 MHz

nIterPerReg = 3

These parameters were used for synthesis:

Input data type: sfix18_en10
Output data type: sfix18_en10
Input dimension: scalar
Automatically select CORDIC maximum shift value based on input word length: on
Number of iterations per pipeline register: 3
Target frequency: 150 MHz
Latency for this configuration: 15

Resource	Usage	Available	Utilization (%)
Slice LUTs	2988	218600	1.37
Slice Registers	1008	437200	0.23
DSPs	0	900	0.00
Block RAM Tile	0	545	0.00
URAM	0	0

	Value
Requirement	6.6667 ns (150 MHz)
Data Path Delay	4.394 ns
Slack	2.266 ns
Clock Frequency	227.24 MHz

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
In R2024b: FlattenHierarchy	Remove PWM Reference Generator block hierarchy from generated HDL code. The default is `inherit`. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

Supports binary-point scaled fixed-point data types only.

Version History

Introduced in R2021a

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R2024b: Custom pipelining, improved latency and resource utilization, optional divide by zero port

Several improvements have been made to the Complex Divide HDL Optimized block:

Custom pipelining is supported via the new CORDIC maximum shift value and Number of iterations per pipeline register parameters.
The latency of this block has been reduced. Latency depends on the specified data type and pipeline configuration. See How to Interface with the Complex Divide HDL Optimized Block for more information.
HDL resource utilization has been further optimized to require fewer hardware resources. See Hardware Resource Utilization for example synthesis results.
An optional divideByZero port has been added to output a flag when the corresponding output is a result of division by zero.

Complex Divide HDL Optimized

Description

Examples

Implement Hardware-Efficient Complex Divide HDL Optimized

Customize Output Value of Real Divide HDL Optimized Block When Denominator Is Zero

Limitations

Ports

Input

num — Numerator scalar | vector | matrix

den — Denominator scalar | vector | matrix

validIn — Whether input is valid Boolean scalar

Output

y — Output computed by dividing inputs complex scalar

Tips

divideByZero — Whether the value at output is the result of division by zero Boolean scalar

Dependencies

validOut — Whether output data is valid Boolean scalar

Parameters

Output datatype — Data type of output fixdt(1,18,10) (default) | single | double | fixdt(1,16,0) | <data type expression>

Programmatic Use

Show divide by zero port — Whether to show the divideByZero port off (default) | on

Programmatic Use

Automatically select CORDIC maximum shift value based on input word length — Automatically select CORDIC maximum shift value based on input word length on (default) | off

Programmatic Use

CORDIC maximum shift value — Maximum shift value of hyperbolic vectoring CORDIC wl - 1 (default) | 10 | positive integer-valued scalar

Dependencies

Tips

Programmatic Use

Number of iterations per pipeline register — Number of CORDIC iterations to perform per pipeline stage 1 (default) | positive integer-valued scalar

Programmatic Use

More About

Tips

Algorithms

CORDIC

Division by Zero Behavior

How to Interface with the Complex Divide HDL Optimized Block

Customizable Pipelining

Hardware Resource Utilization

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

R2024b: Custom pipelining, improved latency and resource utilization, optional divide by zero port

See Also

Blocks

Functions

num — Numerator
scalar | vector | matrix

den — Denominator
scalar | vector | matrix

validIn — Whether input is valid
`Boolean` scalar

y — Output computed by dividing inputs
complex scalar

divideByZero — Whether the value at output is the result of division by zero
`Boolean` scalar

validOut — Whether output data is valid
`Boolean` scalar

Output datatype — Data type of output
`fixdt(1,18,10)` (default) | `single` | `double` | `fixdt(1,16,0)` | `<data type expression>`

Show divide by zero port — Whether to show the `divideByZero` port
`off` (default) | `on`

Automatically select CORDIC maximum shift value based on input word length — Automatically select CORDIC maximum shift value based on input word length
`on` (default) | `off`

CORDIC maximum shift value — Maximum shift value of hyperbolic vectoring CORDIC
`wl - 1` (default) | `10` | positive integer-valued scalar

Number of iterations per pipeline register — Number of CORDIC iterations to perform per pipeline stage
`1` (default) | positive integer-valued scalar

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.