参考设计集成和部署
您可以将生成的 IP 核集成到默认系统参考设计中，或集成到为板注册的自定义参考设计中。HDL Coder™ 可以生成 IP 核，将其集成到 Qsys 工程中，并对硬件进行编程。使用 Embedded Coder®，您可以生成和编译嵌入式软件，并在 ARM® 处理器上运行它。
主题
- Default System Reference Design for Intel FPGA Boards
Learn about the default system reference design and using the reference design for Intel® FPGA boards.
- Default System Reference Design for Intel SoC Devices
Learn about the default system reference design and using the reference design for Intel SoC Devices.
- Default System with External DDR4 Memory Access Reference Design
Learn about the default system with external DDR3 memory access reference design and its requirements.
- Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
精选示例
Use IP Core Generation to Access DUT Registers on Pure Intel FPGA Devices
Use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.
