Reference Design Integration and Deployment

Integrate the generated IP core into the default system reference design

You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board. HDL Coder™ can generate an IP core, integrate it into your Qsys project, and program the hardware. Using Embedded Coder^®, you can generate and build the embedded software, and run it on the ARM^® processor.

Topics

Default System Reference Design for Intel FPGA Boards
Learn about the default system reference design and using the reference design for Intel^® FPGA boards.
Default System Reference Design for Intel SoC Devices
Learn about the default system reference design and using the reference design for Intel SoC Devices.
Default System with External DDR4 Memory Access Reference Design
Learn about the default system with external DDR3 memory access reference design and its requirements.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.

Featured Examples

Use IP Core Generation to Access DUT Registers on Pure Intel FPGA Devices

Use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.