浮点设计
R2026b当您的模型设计使用 Single 或 Double 数据类型时，请使用原生浮点或 FPGA 浮点目标库为 Simulink® 模型生成可综合的 HDL 代码。HDL Coder™ 可以将您的设计映射到原生浮点库和供应商特定的 FPGA 浮点库，例如 Altera® 或 AMD® FPGA 浮点库。
精选示例
Floating Point Support: Field-Oriented Control Algorithm
In this example you review a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM) implemented using single-precision and half-precision floating-point types.
Design Model by Using HDL Coder Native Floating Point and Intel Hard Floating Point
Create a model design that uses both HDL Coder™ native floating-point (NFP) and Intel® hard floating-point (HFP) IP. Using the NFP and HFP blocks together in a mixed design offers better FPGA resource utilizations. For complex models, this mixed design allows you to have bigger design into the FPGA fabric.
Generate HDL Code Using HDL Coder Native Floating Point and AMD Floating Point Library IP
Create a model design that uses both HDL Coder™ native floating-point (NFP) and AMD® floating-point IP. You can use this mixed-design approach to accommodate larger and more complex designs into the FPGA fabric. You can use this hybrid design with AMD floating-point libraries on AMD devices such as Versal, Zynq® UltraScale+™, and more.
