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Native Floating Point

HDL Coder native floating-point, the various features supported, how to model your design, generate HDL code, and verify the generated code

HDL Coder™ native floating-point technology can generate HDL code from your floating-point design. These are some of the key features:

  • Generation of target-independent HDL code that you can deploy on any FPGA or ASIC.

  • Support for the full range of IEEE-754 features including denormal numbers, exceptions, and rounding modes.

  • Extensive support for math and trigonometric blocks.

Floating-point designs have better precision, higher dynamic range, and a shorter development cycle than fixed-point designs. If your design has complex math and trigonometric operations, use native floating-point technology.


createFloatingPointTargetConfigCreate floating-point target configuration for floating-point library that you specify


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Float TypecastTypecast a floating-point type to an unsigned integer or vice versa



Optimize Generated HDL Code for Multirate Designs with Large Rate Differentials

Causes and possible solutions for fixing HDL code generation issues with multirate models that have large rate differentials.