FPGA Floating-Point Libraries

Map to Altera^® and Xilinx^® FPGA floating-point libraries

You can map to a floating-point library to synthesize your floating-point design without converting from a floating-point to fixed-point design. Eliminating this conversion step reduces the loss of data precision and enables you to model a wider dynamic range.

If your model design uses Single or Double data types, use FPGA floating-point target libraries to generate code for your Simulink^® model. HDL Coder™ can map your design to the native floating-point library and a vendor-specific FPGA point library, such as the Altera or Xilinx FPGA floating-point libraries. Using native floating point and vendor-specific IP together more efficiently uses resources on the FPGA, such as hardened DSP floating point adder or multiplier primitives, which allows you to fit a bigger design into the FPGA fabric. This mixed design is advantageous for large and complex models.

Classes

`hdlcoder.FloatingPointTargetConfig`	Floating-point target configuration for floating-point library
`hdlcoder.FloatingPointTargetConfig.IPConfig`	IP settings for selected floating-point configuration

Topics

Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries
How to set up and generate HDL code for Altera and AMD floating-point target libraries.
Customize Floating-Point IP Configuration
Learn how to customize the latency or target frequency of the floating-point IP library.
HDL Coder Support for FPGA Floating-Point Library Mapping
Blocks supported in Simulink for mapping to floating-point target libraries.

Featured Examples

FPGA Floating-Point Library IP Mapping

Use vendor-specific floating-point IP libraries, such as Altera® and Xilinx®, to generate target specific HDL code. For more information on how to map designs to floating-point libraries, see Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries.

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Design Model by Using HDL Coder Native Floating Point and Intel Hard Floating Point

Create a model design that uses both HDL Coder™ native floating-point (NFP) and Intel® hard floating-point (HFP) IP. Using the NFP and HFP blocks together in a mixed design offers better FPGA resource utilizations. For complex models, this mixed design allows you to have bigger design into the FPGA fabric.

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Generate HDL Code Using HDL Coder Native Floating Point and AMD Floating Point Library IP

Create a model design that uses both HDL Coder™ native floating-point (NFP) and AMD® floating-point IP. You can use this mixed-design approach to accommodate larger and more complex designs into the FPGA fabric. You can use this hybrid design with AMD floating-point libraries on AMD devices such as Versal, Zynq® UltraScale+™, and more.

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