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HDL Coder Support for FPGA Floating-Point Library Mapping

In the HDL Coder™ block library, a subset of Simulink® blocks support floating-point library mapping. The subset includes:

  • Blocks that perform basic math operations such as addition, multiplication, and complex trigonometric sine and cosine functions. These blocks map to one or more floating-point IP units on the target FPGA device.

  • Discrete blocks, blocks that perform signal routing, and blocks that perform math operations such as matrix concatenation. These blocks need not map to a floating-point IP unit on the target FPGA device.

Supported Blocks That Map to FPGA Floating-Point Target IP

The following table summarizes the Simulink blocks that can map to FPGA floating-point IP cores.

When mapping to floating-point IP cores, some blocks have mode restrictions.

Note

Some blocks do not map to a floating-point IP core in the third-party hardware. For example, the Abs block maps to an Altera® target IP core but not to a Xilinx® target IP core.

BlockAltera Megafunction IP (ALTFP and ALTERA FP Functions)Xilinx LogiCORE IPAMD® Floating Point Library IPRemarks and Limitations
Abs✓  —
Add✓✓✓—
Bias✓✓ —
Compare To Constant✓✓ —
Compare To Zero✓✓ —
Data Type Conversion✓✓ 

  • Conversions between single and double data types are not supported.

  • Integer rounding mode attribute in the Block Parameters dialog box must be set to Nearest.

  • If you use Altera Megafunction IP for conversion between floating-point and fixed-point data types, the input bitwidth must be between 16 and 128 bits.

Decrement Real World✓✓ —
Discrete FIR Filter✓✓ —
Discrete Transfer Fcn✓✓ —
Discrete-Time Integrator✓✓ —
Divide✓✓ —
Dot Product✓✓  
Gain✓✓✓—
Math Function✓  

  • Set the Function attribute in Block Parameters dialog box to either reciprocal, log or exp.

MinMax✓✓ —
Multiply-Add✓✓ —
Product✓✓✓

  • Product block with more than two inputs is not supported.

Product of Elements✓✓ 

  • The Architecture in HDL Block Properties must be set to Tree.

Reciprocal Sqrt✓  —
Relational Operator✓✓ —
Sqrt✓✓ —
Subtract✓✓✓—
Sum✓✓✓

  • Sum block with - ports is not supported.

  • The block cannot have more than two inputs.

Sum of Elements✓✓ 

  • The Architecture in HDL Block Properties must be set to Tree.

Trigonometric Function✓  

  • Only single data types are supported for floating-point library mapping.

  • In the Block Parameters dialog box, Function must be set to either sin or cos and Approximation method must be set to None.

  • If you are using Altera Quartus 10.1 or 11.0, turn on the AlteraBackwardIncompatibleSinCosPipeline global property using hdlset_param.

Unary Minus✓✓ —

Supported Blocks That Do Not Need to Map to FPGA Floating-Point Target IP

Following are the Simulink blocks that generate HDL code but need not map to an FPGA floating-point IP core.

Limitations for FPGA Floating-Point Library Mapping

  • Complex data types are not supported.

  • The streaming optimization is not supported with floating-point library mapping.

  • The resource sharing optimization is not supported with Unary Minus and Abs blocks.

  • For IP Core Generation, and Simulink Real-Time™ FPGA I/O workflows, your DUT ports cannot use floating-point data types.

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