Decrement Real World
Decrease real-world value of signal by one
Libraries:
Simulink /
Additional Math & Discrete /
Additional Math: Increment - Decrement
HDL Coder /
Math Operations
Description
The Decrement Real World block decreases the real-world value of the signal by one. Overflows always wrap.
Examples
Increment and Decrement Real-World Values
This example shows how to increase and decrease the real-world value of a signal using the following blocks:
Increment Real World
Decrement Real World
Decrement Time To Zero
Decrement To Zero
The Scope block shows the output of a Sine Wave block with amplitude 5, as well as the real-world value of that signal incremented and decremented by one.
The Scope1 block shows the output of a Sine Wave block with amplitude 3, as well as the output of the Decrement To Zero and Decrement Time To Zero blocks:
The Decrement To Zero block decreases the input sine wave signal by one, and ensures the value never goes below zero.
The Decrement Time To Zero block decreases the input sine wave signal by the sample time,
Ts
, and ensures that the value never goes below zero.
Ports
Input
Port_1 — Input signal
scalar | vector | matrix
Input signal, specified as a scalar, vector, or matrix.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fixed point
Output
Port_1 — Output signal
scalar | vector | matrix
Output is the real-world value of the input signal decreased by one. Overflows always wrap. The output has the same data type and dimensions as the input.
Data Types: single
| double
| int8
| int16
| int32
| int64
| uint8
| uint16
| uint32
| uint64
| fixed point
Block Characteristics
Data Types |
|
Direct Feedthrough |
|
Multidimensional Signals |
|
Variable-Size Signals |
|
Zero-Crossing Detection |
|
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
The code generator does not explicitly group primitive blocks that constitute a nonatomic masked subsystem block in the generated code. This flexibility allows for more efficient code generation. In certain cases, you can achieve grouping by configuring the masked subsystem block to execute as an atomic unit by selecting the Treat as atomic unit option.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.
Version History
Introduced before R2006a
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