Decrement Stored Integer

Decrease stored integer value of signal by one

Libraries:
Simulink / Additional Math & Discrete / Additional Math: Increment - Decrement
HDL Coder / Math Operations

Description

The Decrement Stored Integer block decreases the stored integer value of a signal by one.

Floating-point signals also decrease by one, and overflows always wrap.

Examples

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Increment and Decrement Stored Integer Values

Open Model

This example shows how to increase and decrease the stored integer value of a signal by one.

The Increment Stored Integer block increases the stored integer value of the input signal by one.
The Decrement Stored Integer block decreases the stored integer value of the input signal by one.

If you change the value of the input signal to 127 (the maximum value representable by an int8 data type), incrementing the stored integer value by one causes an overflow. Because overflows in the Increment and Decrement Stored Integer blocks always wrap, the Increment Stored Integer block will output a value of -128.

Ports

Input

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Port_1 — Input signal
scalar | vector | matrix

Input signal, specified as a scalar, vector, or matrix.

Output

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Port_1 — Output signal
scalar | vector | matrix

Output is the stored integer value of the input signal decreased by one. Floating-point signals also decrease by one, and overflows always wrap. The output has the same data type and dimensions as the input.

Block Characteristics

Data Types	`double` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`no`
Variable-Size Signals	`yes`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

The code generator does not explicitly group primitive blocks that constitute a nonatomic masked subsystem block in the generated code. This flexibility allows for more efficient code generation. In certain cases, you can achieve grouping by configuring the masked subsystem block to execute as an atomic unit by selecting the Treat as atomic unit option.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

Decrement Stored Integer

Description

Examples

Increment and Decrement Stored Integer Values

Ports

Input

Port_1 — Input signal
scalar | vector | matrix

Output

Port_1 — Output signal
scalar | vector | matrix

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Decrement Stored Integer

Description

Examples

Increment and Decrement Stored Integer Values

Ports

Input

Port_1 — Input signal scalar | vector | matrix

Output

Port_1 — Output signal scalar | vector | matrix

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Port_1 — Input signal
scalar | vector | matrix

Port_1 — Output signal
scalar | vector | matrix

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.