Decrement To Zero

Decrease real-world value of signal by one, but only to zero

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Libraries:
Simulink / Additional Math & Discrete / Additional Math: Increment - Decrement

Description

The Decrement To Zero block decreases the real-world value of the signal by one. The output never goes below zero.

Examples

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Increment and Decrement Real-World Values

Open Model

This example shows how to increase and decrease the real-world value of a signal using the following blocks:

Increment Real World
Decrement Real World
Decrement Time To Zero
Decrement To Zero

The Scope block shows the output of a Sine Wave block with amplitude 5, as well as the real-world value of that signal incremented and decremented by one.

The Scope1 block shows the output of a Sine Wave block with amplitude 3, as well as the output of the Decrement To Zero and Decrement Time To Zero blocks:

The Decrement To Zero block decreases the input sine wave signal by one, and ensures the value never goes below zero.
The Decrement Time To Zero block decreases the input sine wave signal by the sample time, Ts, and ensures that the value never goes below zero.

Ports

Input

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Port_1 — Input signal
scalar | vector | matrix

Input signal, specified as a scalar, vector, or matrix.

Output

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Port_1 — Output signal
scalar | vector | matrix

Output is the real-world value of the input signal decreased by one. The output never goes below zero. The output has the same data type and dimensions as the input.

Block Characteristics

Data Types	`double` \| `fixed point` \| `integer` \| `single`
Direct Feedthrough	`yes`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

The code generator does not explicitly group primitive blocks that constitute a nonatomic masked subsystem block in the generated code. This flexibility allows for more efficient code generation. In certain cases, you can achieve grouping by configuring the masked subsystem block to execute as an atomic unit by selecting the Treat as atomic unit option.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

Decrement To Zero

Description

Examples

Increment and Decrement Real-World Values

Ports

Input

Port_1 — Input signal
scalar | vector | matrix

Output

Port_1 — Output signal
scalar | vector | matrix

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Decrement To Zero

Description

Examples

Increment and Decrement Real-World Values

Ports

Input

Port_1 — Input signal scalar | vector | matrix

Output

Port_1 — Output signal scalar | vector | matrix

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Topics

Port_1 — Input signal
scalar | vector | matrix

Port_1 — Output signal
scalar | vector | matrix

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.