Create Designs Under Test and Test Benches in Simulink and MATLAB
FPGA and ASIC designs contain two components: the design under test (DUT) and the test bench. A DUT is the logic or algorithm to implement on the FPGA or ASIC. A test bench is a framework that instantiates the DUT and applies test stimuli that verify the DUT. You can create the DUT and test bench in either MATLAB® or Simulink®.
This table shows the differences between a DUT and a test bench:
| Component | Description | Purpose | Example | How to Design in Simulink and MATLAB |
|---|---|---|---|---|
| Design Under Test (DUT) | Develop logic for hardware implementation | Generate HDL code | If you are building a digital filter, the filter algorithm is the DUT. |
|
| Test Bench | To run stimuli and checks that are not part of the hardware implementation | Simulate and validate the DUT | The associated test bench feeds a range of input signals to the digital filter algorithm and compares the algorithm output with expected results. |
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Create a DUT and Test Bench in Simulink
In Simulink, a DUT can be:
An entire Simulink model, including a model or subsystem reference
A Simulink subsystem
You can use only supported blocks in the DUT. For more information, see hdllib.
In Simulink, the test bench consists of Simulink blocks in the model that are not included in the DUT. The test bench creates input test data for the Simulink subsystem that is the DUT and then processes the DUT output data. If the DUT is the entire Simulink model, the model does not contain a test bench. A test bench is required to generate an HDL test bench to verify the HDL code in an HDL simulator. For more information on verifying generated HDL code with an HDL test bench, see Test Bench Generation.
Because you do not generate HDL code from the test bench, you can use any Simulink block in the test bench.
For more guidelines on how to create a DUT in Simulink, see DUT Subsystem Guidelines.
For more information on partitioning a model into a DUT and a test bench, see Partition Model into DUT and Test Bench.
Create a DUT and Test Bench in MATLAB
In MATLAB, you create the DUT as a MATLAB function and the test bench as a MATLAB script. The MATLAB test bench creates input test data, invokes the MATLAB function that is the DUT, and then processes the DUT output data.
You can use only supported MATLAB language constructs in the code for the DUT. See Functions Supported for HDL and HLS Code Generation. Because you do not generate HDL code from the test bench, you can use any MATLAB language construct in the test bench.
For more information on MATLAB test bench requirements and best practices, see Using Test Benches With HDL and HLS Code Generation.
