HDL Coder 快速入门
HDL Coder™ 通过从 MATLAB® 函数、Simulink® 模型和 Stateflow® 图生成可移植、可综合的 Verilog®、SystemVerilog 和 VHDL® 代码，支持 FPGA、SoC 和 ASIC 的高层设计。您可以将生成的 HDL 代码用于 FPGA 编程、ASIC 原型构建和生产设计。
HDL Coder 包括工作流顾问，可用于在 Xilinx®、Intel® 和 Microchip 板上通过生成的代码自动进行原型构建，并为 ASIC 和 FPGA 工作流生成 IP 核。您可以针对速度和面积进行优化，突出显示关键路径，并在综合之前生成资源利用率估计值。HDL Coder 提供 Simulink 模型与生成的 Verilog、SystemVerilog 和 VHDL 代码之间的可追溯性，因而支持对遵循 DO-254 及其他标准的高完整性应用进行代码验证。
教程
- 创建 HDL 兼容的 Simulink 模型
创建一个模型并检查 HDL 代码生成的兼容性。 - 从 Simulink 模型生成 HDL 代码
从 Simulink 模型生成 VHDL、Verilog 和 SystemVerilog 代码。 - Verify Generated HDL Code from Simulink Model
Generate an HDL test bench to verify the VHDL or Verilog Code. - HDL Code Generation and FPGA Synthesis from Simulink Model
Generate code and synthesize your Simulink design on the target FPGA. - Create HDL- or HLS-Compatible MATLAB Algorithms
Create an HDL- or HLS-compatible MATLAB algorithm and MATLAB test bench and verify algorithm functionality. - Generate HDL Code from MATLAB Algorithms
Use the HDL Workflow Advisor to generate HDL code from MATLAB algorithms. - Synthesize Generated HDL Code from MATLAB Algorithms
Use a third-party synthesis tool to synthesize generated HDL code for target hardware.
Simulink 到 HDL
MATLAB 到 HDL
关于 HDL 代码生成
- Choose to Generate HDL Code in Simulink or MATLAB
Choose between a Simulink or MATLAB design environment for your HDL Coder project.
- 基本 HDL 代码生成工作流
遵循从 MATLAB 和 Simulink 算法进行 HDL 代码生成和 FPGA 综合的工作流。
- Create Designs Under Test and Test Benches in Simulink and MATLAB
Partition your design into a design under test and test bench in Simulink or MATLAB.
- Choose Fixed- or Floating-Point Data Types When Generating HDL Code
To balance precision and hardware resources, choose to use fixed-point, floating-point, or a mixed use of both data types in your design.
- Workflows in HDL Workflow Advisor
Learn about the HDL Workflow Advisor and various workflows you can choose and platforms you can target.
- Introduction to Optimizations in HDL Coder
Learn about speed and area optimizations and how to optimize your design.
精选示例
Get Started with MATLAB to High-Level Synthesis Workflow Using HDL Coder App
Generate High-Level Synthesis (HLS) code from MATLAB code by using the HDL Coder App.
Generate HDL Code from Stateflow Charts
Model a counter in Stateflow, apply HDL‑compatible chart settings, and generate synthesizable HDL code.
Get Started with IP Core Generation from Simulink Model
Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® ZC702 evaluation kit.
Get Started with IP Core Generation from MATLAB Function
Use the MATLAB® HDL Workflow Advisor to generate a customized IP core that blinks LEDs on an FPGA board. This example deploys the generated IP core on the ZedBoard hardware, but you can use any Xilinx® Zynq® platform or Xilinx FPGA with a MicroBlaze processor.
Real-Time Simulation of Modular Multilevel Converter on FPGA
Model a modular multilevel converter with half-bridge power modules by using generic switching-function modeling approach, generate HDL code and deploy onto a target hardware.
视频
HDL Coder 概述
使用 HDL Coder 生成用于 FPGA 和 ASIC 设计的 VHDL 和 Verilog 代码
使用 Simulink 在 FPGA 或 ASIC 上部署 MATLAB 算法
了解如何通过 Simulink、Fixed-Point Designer™ 和 HDL Coder 采用 MATLAB DSP 算法并以 FPGA 或 ASIC 为目标
