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Create HDL-Compatible Simulink Model

This example illustrates how you can create a Simulink® model for HDL code generation. To create a MATLAB® algorithm compatible for HDL code generation, see Guidelines for Writing MATLAB Code to Generate Efficient HDL and HLS Code.

The model is a simple counter algorithm that counts upward and wraps back to zero after it reaches the upper limit that you specify. To open the model directly without performing the steps, see Simple Counter Model.

Use Blank DUT Template

To create a HDL-compatible Simulink model, use the Blank DUT template. The template is preconfigured for HDL code generation by using the hdlsetup function.

  1. On the MATLAB toolstrip, click the Simulink button.

  2. In the Simulink Start Page, navigate to the HDL Coder section, and then select the Blank DUT template.

  3. Save the model with the file name hdlcoder_simple_up_counter.slx in a working folder that is writable.

Simple counter model that has subsystem named HDL_DUT.

The Blank DUT template has a HDL_DUT subsystem that corresponds to the Design-Under-Test (DUT) for which you generate HDL code. To verify the DUT functionality, the template contains a test bench outside the HDL_DUT subsystem that provides inputs to the DUT and logs output values. See Partition Model into DUT and Test Bench.

Choose Blocks from HDL Coder Library

To design your counter algorithm, use blocks from the HDL Coder Block Library. Blocks in this library are preconfigured for HDL code generation. To filter the Simulink Library Browser to show block libraries that support HDL code generation:

  1. On the Apps tab, select HDL Coder.

  2. From the HDL Code tab, select HDL Block Properties > Open HDL Block Library.

Alternatively, at the command line, enter hdllib.

hdllib

Simulink Library Browser that shows the HDL Coder compatible blocks.

Blocks in the HDL Coder Library are available with Simulink. If you do not have HDL Coder™, you can simulate the blocks in your model, but cannot generate HDL code.

You can find additional HDL-supported blocks in these block libraries:

  • DSP System Toolbox HDL Support

  • Communications Toolbox HDL Support

  • Vision HDL Toolbox

  • Wireless HDL Toolbox

To restore the Library Browser to the default view, in the Library Browser, click the exit HDL-compatible blocks mode button. Alternatively, at the command line, enter:

hdllib('off')

Develop Algorithm for DUT

  1. Double-click the HDL_DUT subsystem. Drag blocks from the HDL Coder library to your model. This table lists the blocks to add to your model for designing the counter. To learn about what a block does and to specify its block parameters, double-click the block.

    BlockLibraryNumber of BlocksBlock Parameters
    ConstantSources2

    • Constant values: 1 and 0

    • Output data type: uint8

    SwitchSignal Routing2Criteria for passing first input: u2 > Threshold
    DelayDiscrete2Delay length: 1
    SumMath Operations1Accumulator data type: Inherit: Same as first input
    Relational OperatorLogic and Bit Operations1Relational operator: >

  2. Rename the input ports In1 and In2 to count_threshold and Enable respectively. Place the blocks in your model and connect them.

    HDL_DUT Subsystem to model simple up counter. The subsystem has two input named, Enable and count_threshold.

The Enable signal specifies whether the counter counts upward from the previous value. When the Enable signal is logical high, the counter counts up from zero to the count_threshold value. When the value of out becomes equal to the count_threshold value, the counter wraps back to zero and starts counting again. When the Enable signal becomes logical low, the counter holds the previous value.

Create Test Bench for Design

Navigate to the top level of the model and change the input settings.

  • Constant block input to count_threshold: This input indicates the maximum value up to which the counter counts. This example shows how to design a 4-bit up counter. Set the Constant value to 15 (2^4 - 1), and set the Output data type to uint8.

    The output data type of this Constant block then matches the output data type of the Constant blocks inside the HDL_DUT subsystem.

  • Counter Free-Running block input to Enable: Remove the Counter Free-Running block. Replace this block with a Constant block that has a value of 1, Output data type set to boolean, and Sample time of 1.

HDL_DUT subsystem with ports connected to inputs and display.

See also Create a Simple Model.

The preceding section shows the hdlcoder_simple_up_counter.slx model that you created by following the steps described above. To open the model in MATLAB, click the Open Model button.

Simple Counter Model

Open Model

Open this model to see a simple counter. The model counts up from zero to a threshold value and then wraps back to zero. The threshold value is set to 15. To change the threshold value, change the value of the input to the count_threshold port. The Enable signal specifies whether the counter counts upward or holds the previous value. A value of 1 indicates that the counter counts upward continuously.

Simulate and Verify Design Functionality

Set the Stop time of the model to 50. Simulate your model by clicking the button. To see the simulation results, open the Scope block at the top level of your model.

The simulation results display the Enable signal generating a constant value of 1. The out signal counts from 0 to 15, wraps back to zero, and then counts up again.

display of Ramp signal with uniform step increments.

Generate HDL Code from Simulink Model

Before you generate HDL code, you can verify that the model settings are compatible for HDL code generation. The counter model used in this example is compatible for HDL code generation. To verify and update your model for HDL compatibility, use the HDL Code Advisor. See Check HDL Compatibility of Simulink Model Using HDL Code Advisor.

See Generate HDL Code from Simulink Model.

See Also

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