HDL Language Support and Supported Third-Party Tools and Hardware

VHDL, Verilog, and SystemC Language Support

The generated HDL code complies with the following standards:

VHDL-1993 (IEEE^® 1076-1993)
Verilog-2001 (IEEE 1364-2001)
SystemVerilog-2005 (IEEE 1800-2005)
SystemC 2.3 (IEEE 1666-2011)

Third-Party Synthesis Tools and Version Support

The HDL Workflow Advisor is tested with the following third-party FPGA synthesis tools:

Intel^® Quartus^® Prime Standard 22.1.1
Intel Quartus Pro 22.4
Xilinx^® Vivado^® Design Suite 2023.1
Microchip Libero^® SoC 2022.1
Xilinx ISE 14.7
Cadence^® Stratus HLS 22.02
Cadence Genus 19.16

When you use a synthesis tool that has been tested with the HDL Workflow Advisor and start the workflow, the Advisor generates a list of devices that are supported with that tool. If you use a third-party synthesis tool that is not tested with HDL Workflow Advisor, the Advisor does not update the device list to reflect the FPGA devices that you can use for that tool.

For example, the HDL Workflow Advisor has been tested with Intel Quartus Prime Standard and Intel Quartus Pro. If you use a tool has not been tested with the Advisor, such as Intel Quartus Prime Lite, the FPGA device list does not get updated in the Workflow Advisor.

To use third-party synthesis tools with HDL Coder™, a supported synthesis tool must be installed, and the synthesis tool executable must be on the system path. For details, see Tool Setup.

FPGA-in-the-Loop Hardware

The FPGAs supported for FPGA-in-the-loop simulation with HDL Verifier™ are listed in the HDL Verifier documentation.

You can also add custom FPGA boards by using the FPGA Board Manager. See FPGA Board Customization (HDL Verifier) for details.

For FPGA-in-the-Loop or Customization for USRP™ Device using the HDL Workflow Advisor, a supported synthesis tool must be installed, and the synthesis tool executable must be on the system path. For details, see Tool Setup.

Generic ASIC/FPGA Hardware

The following hardware is supported for the Generic ASIC/FPGA workflow:

Synthesis Tool	Device Family
Xilinx Vivado	Kintex^® 7
	Artix^® 7
	Artix UltraScale+™
	Kintex UltraScale+
	KintexU
	Spartan^® 7
	Virtex^® UltraScale+
	Virtex UltraScale+ HBM
	Virtex UltraScale+ 58G
	Virtex7
	VirtexU
	Zynq^®
	Zynq UltraScale+
	Zynq Ultrascale+ RFSoC
	Versal AI Core
Xilinx ISE	Virtex6
	Virtex5
	Virtex4
	Spartan-3A DSP
	Spartan 3E
	Spartan3
	Spartan6
Altera^® Quartus II Note Altera Quartus II refers to the synthesis tool Intel Quartus Prime Standard.	Cyclone^® IV
	Cyclone V
	Arria^® II GX and GZ
	Stratix^® IV
	Stratix V
	Arria 10
	Arria V GX
	MAX 10
	Cyclone 10 LP
Intel Quartus Pro	Arria 10
	Cyclone 10 GX
	Stratix 10
	Intel Agilex^®
Microchip Libero SoC	SmartFusion2
	RTG4
	IGLOO2
	PolarFire
	PolarFire SoC

IP Core Generation Hardware

The following hardware is supported for the IP Core Generation workflow:

Synthesis Tool	Target Platform
Xilinx Vivado	ZedBoard FMC-HDMI-CAM
	ZedBoard and FMCOMMS2/3/4/
	ZC706 FMC-HDMI-CAM
	ZC706 FMCOMMS2/3/4/
	ZC706 and FMCOMMS5
	ZC702 FMC-HDMI-CAM
	ZCU102 FMC-HDMI-CAM
	ZCU102 and FMCOMMS2/3/4
	ZCU106 IMX274MIPI-FMC
	ZCU106 FMC-HDMI-CAM
	Zynq ZC706 evaluation kit
	Zynq ZC702 evaluation kit
	PicoZed FMC-HDMI-CAM
	Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit
	Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit
	Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit
	Kintex-7 KC705 development board
	Artix-7 35T Arty development board
	Versal AI Core Series VCK190 Evaluation Kit
	Virtex-7 VC707 development board
Intel Quartus Pro	Intel Arria 10 SoC development kit
Altera Quartus II Note Altera Quartus II refers to the synthesis tool Intel Quartus Prime Standard.	Intel Arria 10 SoC development kit
	Cyclone V SoC development kit Rev. C and Rev. D
	Arrow DECA Max 10 FPGA development board
	Arrow SoC Kit development board
	Arria 10 GX FPGA development kit
Microchip Libero SoC	Microchip Polarfire^® SoC Icicle Kit

Simulink Real-Time FPGA I/O: Speedgoat Target Computer

You use the Simulink Real-Time FPGA I/O workflow to target Speedgoat FPGA I/O modules. These I/O modules are part of Speedgoat^® target computer systems. To run the Simulink Real-Time FPGA I/O workflow, install the Speedgoat I/O Blockset and the Speedgoat HDL Coder Integration Packages. After you install the integration packages, you can choose the Target platform and then run the workflow to generate a Simulink^® Real-Time™ interface subsystem.

To learn about:

The integration packages and how you can install them, go to HDL Coder Integration Packages documentation online at www.speedgoat.com/knowledge-center. Follow the instructions to download and install the Speedgoat - HDL Coder Integration Packages under Getting Started.
Speedgoat I/O modules that are supported with the HDL Workflow Advisor, see Speedgoat Real-Time FPGA Application Support from HDL Coder.

See Speedgoat FPGA Support with HDL Workflow Advisor.