HDL Applications for Signal Processing Algorithms

Create and run HDL applications using DSP HDL Toolbox™ and DSP System Toolbox™ blocks

This section contains algorithms and HDL applications that you can develop by using blocks from DSP HDL Toolbox, and blocks from DSP System Toolbox that are supported for HDL code generation. DSP HDL Toolbox provides blocks and System objects that implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. The DSP HDL Toolbox blocks and System objects also have high-throughput streaming interfaces that achieve gigasamples-per-second (GSPS), also called super sample rates, hardware control signals, and options to select different hardware implementations of their algorithms. The DSP System Toolbox product provides algorithms, apps, and scopes for designing, simulating, and analyzing signal processing systems.

To filter the Simulink Library Browser to show only libraries that contain HDL-supported blocks, enter hdllib. For filtered lists of DSP HDL Toolbox and DSP System Toolbox blocks supported for HDL code generation, see DSP HDL Toolbox Block List (HDL Code Generation) (DSP HDL Toolbox) and DSP System Toolbox Block List (HDL Code Generation) (DSP System Toolbox), respectively.

Functions

hdllib Display blocks that are compatible with HDL code generation

Related Information

DSP HDL Toolbox
DSP System Toolbox

Featured Examples

High-Throughput Channelizer for FPGA

Implement a high-throughput channelizer for hardware by using a polyphase filter bank.

Open Script

Implement Digital Downconverter for FPGA

Design a digital down-converter (DDC) for radio communication applications.

Open Script

Implement Digital Upconverter for FPGA

Design a digital upconverter (DUC) for radio communication applications such as LTE, and generate HDL code.

Open Script

Programmable FIR Filter for FPGA

Implement a programmable FIR filter for hardware. You can program the filter to the required response by loading the coefficients into internal registers using a memory-style interface.

Open Model

Multichannel FIR Filter for FPGA

Implement a discrete FIR filter with multiple input data streams for hardware.

Open Script

FPGA-Based Monopulse Technique: Algorithm Design

Develop a monopulse technique to perform digital downconversion on hardware (Part 1).

(DSP HDL Toolbox)

Rectangular Array MVDR Beamformer

Implement a minimum-variance distortionless-response (MVDR) beamformer for a 4x4 rectangular antenna array on FPGA.

(DSP HDL Toolbox)