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Clock input port

Name for clock input port

Model Configuration Pane: Global Settings


Specify the name for the clock input port in generated HDL code.


clk (default) | character vector

Default: clk

Enter the clock signal name in generated HDL code as a character vector.

For a generated entity my_filter, if you specify 'filter_clock' as the clock signal name, the entity declaration is as shown in this code snippet:

ENTITY my_filter IS
   PORT( filter_clock   :  IN  std_logic;
         clk_enable     :  IN  std_logic;
         reset          :  IN  std_logic;
         my_filter_in   :  IN  std_logic_vector (15 DOWNTO 0); -- sfix16_En15
         my_filter_out  :  OUT std_logic_vector (15 DOWNTO 0); -- sfix16_En15
END my_filter;


If you specify a VHDL®, Verilog® or SystemVerilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL, Verilog or SystemVerilog identifier. For example, if you specify the reserved word signal, the resulting name string would be signal_rsvd.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.


  • Pass the property as an argument to the makehdl function.


Recommended Settings

No recommended settings.

Programmatic Use

Parameter: ClockInputPort
Type: character vector
Value: A valid identifier in the target language
Default: 'clk'

Version History

Introduced in R2012a

See Also