引导式代码生成

使用“配置参数”对话框和 Simulink HDL 工作流顾问进行引导式代码生成

您可以通过 UI 使用 Simulink® 工具条中的 HDL 代码选项卡或“配置参数”对话框生成 Simulink 模型的 HDL 代码。在此对话框中，您可以指定各种 HDL 代码生成设置，包括基本文件夹、语言选择以及更高级优化参数。要了解如何从 HDL 代码选项卡生成 HDL 代码，请参阅Generate HDL Code from Simulink Model。

要将生成的代码部署到目标设备，请使用 Simulink HDL 工作流顾问。该顾问可运行端到端工作流，以检查 HDL 兼容性并将生成的代码部署到目标设备。HDL 工作流顾问在 Simulink Online™ 中不可用。

函数

hdladvisorDisplay HDL Workflow Advisor
hdlsetupSet model configuration parameters for HDL code generation
hdlsetuptoolpathSet up system environment to access FPGA synthesis software

检查

HDL Coder Checks in Model Advisor / HDL Code Advisor Overview
Check for global reset setting for Xilinx and Altera devices
Check algebraic loops

模型设置

全部展开

要生成 HDL 的模块Select the subsystem or model for HDL code generation
语言Specify HDL code generation language
代码生成文件夹Specify target folder for generated HDL code
还原模型默认值Reset model-level HDL settings to the default values
运行兼容性检查器Check subsystem compatibility for HDL code generation
生成Generate HDL code for subsystem or model
工作流Specify the target workflow
工程文件夹Folder specification for workflow-specific files (自 R2023b 起)
目标平台Specify where to deploy generated HDL code (自 R2023b 起)
综合工具Specify the synthesis tool for targeting the generated HDL code
系列Specify target device chip family for the model
设备Specify target device name
包Specify target device package name
速度Specify target device speed value
参考设计Configuration parameters to customize reference design (自 R2023b 起)
参考设计工具版本Display of reference design tool version (自 R2023b 起)
忽略工具版本不匹配Warning in instances of reference design tool version mismatch (自 R2023b 起)
参考设计参数Parameters available for default reference designs (自 R2023b 起)
目标频率Specify target frequency for multiple features and workflows

常规

将流水线延迟映射到 RAMMap pipeline registers in the generated HDL code to RAM
RAM 映射阈值Specify the minimum RAM size for mapping to block RAMs
变换非零初始值延迟Specify Transform Delay blocks to have zero initial value
删除未使用的端口Remove unused ports from the design
基于使能的约束Meet the timing requirement of the multicycle path in your model

流水线

允许设计延迟分布Whether to allow distributed pipelining and delay absorption optimizations to move design delays
流水线分布优先级Priority for the distributed pipelining and delay absorption optimizations
时钟频率流水线Insert pipeline registers at a clock rate that is faster than the data rate
允许 DUT 输出端口的时钟频率流水线Produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate
平衡时钟频率流水线 DUT 输出端口Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs (自 R2022b 起)
分布式流水线Enable pipeline register distribution
使用综合估计执行分布式流水线Determine more accurate propagation delays for each component (自 R2022a 起)
自适应流水线Insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device
将查找表映射到 RAM Lookup tables in your design to block RAM and reduce area usage on the target FPGA device (自 R2021b 起)

资源复用

复用加法器Share adders with the resource sharing optimization
加法器复用最小位宽Specify the minimum bit width that is required to share adders with the resource sharing optimization
复用乘法器Share multipliers with the resource sharing optimization
乘法器复用最小位宽Specify the minimum bit width that is required to share multipliers with the resource sharing optimization
乘法器提升阈值Share smaller multipliers with other larger multipliers by using the resource sharing optimization
乘法器分割阈值Partition multipliers based on a threshold
Multiply-Add 模块Share Multiply-Add blocks with the resource sharing optimization (自 R2021a 起)
Multiply-Add 模块复用最小位宽Specify the minimum bit width that is required to share Multiply-Add with the resource sharing optimization (自 R2021a 起)
原子子系统Share Atomic Subsystem blocks with the resource sharing optimization
MATLAB Function 模块Share MATLAB Function blocks with the resource sharing optimization
浮点 IPShare floating-point IPs in the design

帧到采样的转换

启用帧到采样的转换Enable frame-to-sample conversion (自 R2022b 起)
每周期采样数Specify the size of the signals after the frame-to-sample conversion streams them (自 R2022b 起)
输入 FIFO 大小Specify the register size of the generated input FIFOs around the streaming matrix partitions (自 R2022b 起)
输出 FIFO 大小Specify the register size of the generated output FIFOs around the streaming matrix partitions (自 R2022b 起)
输入处理顺序Choose between row-major and column-major ordering for the frame inputs (自 R2023a 起)
启用外部存储的延迟大小阈值(位)Specify a threshold size in kilobytes to map large integer delays to input and output DUT ports and offload large delays to external memory outside of your FPGA (自 R2023a 起)
使用浮点Specify use of native floating-point library (自 R2023a 起)
延迟策略Specify minimum or maximum latency
处理非正规数Specify whether to handle denormal numbers
尾数乘法策略Specify how to implement the mantissa multiplication operation
供应商特定浮点库Select vendor-specific floating-point library (自 R2023a 起)

全局设置

复位类型Reset logic for registers in HDL code
复位生效电平Asserted or active level of the reset input signal
时钟输入端口Name for clock input port
时钟使能输入端口 Name for clock enable input port
复位输入端口Name for reset input port
时钟输入Generate single or multiple clock inputs
将 Simulink 速率视为实际硬件速率Oversampling value based on model rates (自 R2023b 起)
时钟沿Active clock edge
过采样因子Oversampling value

常规

Verilog 文件扩展名File name extension for generated Verilog files
VHDL 文件扩展名File name extension for generated VHDL files
SystemVerilog 文件扩展名File name extension for generated SystemVerilog files (自 R2023b 起)
包后缀Text to append to model or subsystem name
实体冲突后缀Text to resolve duplicate module names
分割实体文件后缀Text to be appended to model name to form name of generated entity file
保留字后缀Text to append to value names, postfix values, or labels
分割架构文件后缀Text to be appended to model name to form name of generated architecture file
钟控过程后缀Postfix as character vector
分割实体和架构Number of files entity and architecture code is written to
复数实部后缀Text to append to real part of complex signal names
VHDL 架构名称Architecture name for DUT
复数虚部后缀Text to append to imaginary part of complex signal names
模块名称前缀Prefix for module or entity name
使能前缀Base name as character vector
时序控制器后缀Postfix as character vector
流水线后缀Text to append to names of input or output pipeline registers
VHDL 库名称Target library name for generated VHDL code
将为模型引用生成的 VHDL 或 SystemVerilog 代码置于单一库中Code placement for model references
模块生成标签Postfix to block labels used for HDL GENERATE statements
输出生成标签Postfix to output assignment block labels
实例生成标签Text to append to instance section labels
向量前缀Prefix to vector names
实例前缀Prefix to generated component instance names
实例后缀Postfix to generated component instance names
映射文件后缀Postfix appended to file name for generated mapping file

端口

输入数据类型HDL data type for the input ports of the model
输出数据类型HDL data type for the output ports of the model
时钟使能输出端口Name for the generated clock enable output port
尽量减少时钟使能Minimize clock enable logic
尽量减少全局复位Minimize reset logic
使用触发信号作为时钟Trigger input signal
生成可调参数的 HDL DUT 输入端口Enable creation of DUT input ports for tunable parameters (自 R2021b 起)
平衡生成的 DUT 输入端口的延迟Insert matching delays on generated DUT inport port paths (自 R2022b 起)
生成测试点的 HDL DUT 输出端口Enable creation of DUT output ports for the test point signals
平衡生成的 DUT 输出端口的延迟Insert matching delays on generated DUT output port paths (自 R2022b 起)
端口标量化Vector ports flattened into scalar ports
FPGA 部署的最大 I/O 引脚数Maximum number of I/O pins for target FPGA (自 R2022a 起)
检查 DUT 引脚数是否超出 I/O 阈值Message generated when DUT pin count exceeds maximum number of I/O pins (自 R2023a 起)

编码风格

通过聚合体表示常量值Constants represented by aggregates
内联 MATLAB Function 模块代码Inline HDL code for MATLAB Function blocks
初始化所有 RAM 模块Generate initial signal value for RAM blocks
RAM 架构RAM architecture with or without clock enable
无复位寄存器初始化Initialize registers without reset and mode of initialization
尽量减少中间信号Optimize HDL code for debuggability or code coverage
展开 For-Generate 循环Unroll and omit FOR and GENERATE loops from generated HDL code
从封装子系统生成参数化 HDL 代码Generate reusable HDL code for subsystems
枚举类型编码方案Encoding scheme represent enumeration types
对寄存器使用 "rising_edge/falling_edge" 样式Specify if generated should code use rising_edge function or falling_edge function
代码重用Single reusable file to represent the subsystem logic (自 R2022a 起)
内联 VHDL 配置Specify if generated VHDL code includes inline configurations
串联类型安全零Syntax for concatenated zeros in generated VHDL code
生成经过混淆处理的 HDL 代码Specify generation of obfuscated HDL code
在生成的 HDL 代码中保留总线结构体Generate code with VHDL record or SystemVerilog structure types (自 R2022b 起)
标量化端口命名的索引Starting index for the names of scalarized vector ports (自 R2022a 起)
优化时序控制器Timing controller entity for speed and code size
时序控制器架构Architecture of generated timing controller
使用 Verilog 或 SystemVerilog 的 `timescale 指令Use of compiler directives in generated Verilog or SystemVerilog code
Verilog 或 SystemVerilog 的 timescale 设定Timescale to use in generated Verilog or SystemVerilog code

编码标准

HDL 编码标准Enable the Industry coding standard guidelines
在编码标准报告中显示通过规则Filter the coding standard report so passing rules do not appear
检查重复名称Check for duplicate names in the design
检查设计名称中是否有 HDL 关键字Check for HDL keywords in design names
检查模块、实例和实体名称长度Specify whether to check module, instance, and entity name length
检查信号、端口和参数名称长度Specify whether to check signal, port, and parameter name length
检查时钟使能信号Specify whether to check for clock enable signals in the generated code
检测复位信号的使用Specify whether to check for reset signals in the generated code
检测异步复位信号的使用Specify whether to check for asynchronous reset signals in the generated code
尽量减少变量的使用Specify whether to minimize use of variables
检查设置 RAM 初始值的初始语句Specify whether to check for initial statements that set RAM initial values
检查 process 中的条件语句Specify whether to check for length of conditional statements
检查多个级联控制区域中相同变量的赋值Specify whether to check if there are assignments to same variable in multiple cascaded control regions (自 R2021b 起)
检查 if-else 语句链长度Specify whether to check if-else statement chain length
检查 if-else 语句嵌套深度Specify whether to check if-else statement nesting depth
检查乘法器宽度Specify whether to check multiplier bit width
检查非整数常量Specify whether to check for non-integer constants
检查换行长度Specify whether to check line lengths in the generated HDL code

注释

启用注释Enable or disable comments
头部注释Comment lines in header of generated HDL and test bench files
在头部包括时间/日期戳Time and date information in the generated HDL file header
在模块注释中包含需求Generation of requirements comments
自定义文件头部注释Custom file header comment
自定义文件尾部注释Custom file footer comment

模型生成

生成的模型Enable or disable generation of generated model
验证模型Enable or disable generation of a validation model
验证模型的后缀Suffix of the validation model name
生成的模型的前缀Prefix of the generated model name
布局样式Layout style of the generated HDL model (自 R2021b 起)
自动信号布线Automatic routing of signals in the generated model
模块间水平缩放Horizontal scaling of generated model
模块间垂直缩放Vertical scaling of generated model

高级

检查黑盒接口中是否存在名称冲突Specify whether to check for duplicate module or entity names
检查生成的 HDL 代码中是否存在实数Specify whether to check for reals in the generated HDL code
生成 HDL 代码Enable or disable HDL code generation for model or Subsystem
通过生成仅仿真索引检查来抑制越界访问错误Logic that runs during simulation time to prevent array indices from going out of bounds (自 R2022a 起)
生成可追溯性报告Generate report with hyperlinks from code to model and model to code
可追溯性样式Designation of line-level or comment-based traceability
生成模型 Web 视图Web view to navigate between code and model
生成资源利用率报告Generate report with resource utilization information
生成优化报告Generate report about impacts of HDL Coder optimizations
生成高级时序关键路径报告Generate a report that shows estimated critical path in models
自定义时序数据库目录Path to load custom timing (自 R2021b 起)
仿真工具Simulator for running generated test benches
HDL 代码覆盖率Enable or disable HDL code coverage flags in generated simulator scripts
HDL 测试平台Enable or disable HDL test bench generation
联合仿真模型Enable or disable generation of cosimulation model
SystemVerilog DPI 测试平台Enable or disable SystemVerilog DPI test bench generation
测试平台名称后缀Specify suffix appended to test bench name
强制时钟Specify whether the test bench forces clock input signals
时钟高电平时间(ns)Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1)
时钟低电平时间(ns)Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0)
保持时间(ns)Specify a hold time, in nanoseconds, for input signals and forced reset input signals
强制时钟使能Specify whether the test bench forces clock enable input signals
时钟使能延迟(以时钟周期为单位)Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable
强制复位Specify whether the test bench forces reset input signals
复位长度(以时钟周期为单位)Define length of time (in clock cycles) during which reset is asserted
保持采样之间的输入数据Specify how long subrate signal values are held in valid state
初始化测试平台输入Specify initial value driven on test bench inputs before data is asserted to DUT
多文件测试平台Divide generated test bench into helper functions, data, and HDL test bench code files
测试平台数据文件名后缀Specify suffix added to test bench data file name when generating multi-file test bench
测试平台参考后缀Specify character vector to be appended to names of reference signals generated in test bench code
使用文件 I/O 读取/写入测试平台数据Create and use data files for reading and writing test bench input and output data
忽略输出数据检查(采样数)Specify number of samples during which output data checking is suppressed
浮点容差检查依据Specify the floating-point tolerance check option
容差值Enter the tolerance value based on the floating-point tolerance check setting that you specify
仿真库路径Specify the path to your compiled Altera or Xilinx simulation libraries
生成 EDA 脚本Script files for third-party electronic design automation (EDA) tools
编译文件后缀Postfix to append to the DUT or test bench name to form the compilation script file name
编译初始化Format name used to write the Init section of the compilation script
编译 VHDL 的命令Format name used to write the Cmd section of the compilation script
编译 Verilog 或 SystemVerilog 的命令Format name used to write the Cmd section of the compilation script
编译终止Format name used to write the termination portion of the compilation script
仿真文件后缀Postfix to append to the DUT or test bench name
仿真初始化Format name used to write the initialization section of the simulation script
仿真命令Format name used to write the simulation command
仿真波形查看命令Waveform viewing command written to simulation script
仿真终止Format name used to write the termination portion of the simulation script
仿真器标志Simulator flags to apply to generated compilation scripts
选择综合工具Generation of synthesis scripts
综合文件后缀Postfix to append to file name
综合初始化Format name used to write initialization section of synthesis script
综合命令Format name used to write the synthesis command
综合终止Format name that is used to write termination portion of synthesis script
要添加到综合工程的附加文件Additional HDL or constraint files
选择 HDL lint 工具Generation of an HDL lint script
Lint 初始化Initialization text
Lint 命令Command for HDL lint script
Lint 终止Termination character vector

主题

使用 HDL 工作流顾问

使用“模型配置参数”对话框

模型配置参数