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Minimize global resets

Minimize reset logic

Model Configuration Pane: Global Settings / Ports


Omit generation of reset logic in the HDL code.


If you select Minimize global resets, the generated HDL code contains registers that do not have a reset port. If you do not initialize these registers, there can be potential numerical mismatches in the HDL simulation results. To avoid simulation mismatches, you can initialize the registers by using the No-reset registers initialization setting.

By default, the No-reset registers initialization setting has the value Generate initialization inside module, which means that the code generator initializes the registers as part of the HDL code generated for the DUT. To initialize the registers with the script, set No-reset registers initialization to Generate an external script. You must use a zero initial value for the blocks in your Simulink® model.

This option is ignored, when the HDL Coding Standard is set to Industry.


off (default) | on

Default: Off


When you enable this setting, the code generator tries to minimize or remove the global reset logic from the HDL code. This code snippet corresponds to the Verilog® code generated for a Delay block in the Simulink model. The code snippet shows that HDL Coder™ removed the reset logic.

 always @(posedge clk)
    begin : Delay_Synchronous_process
      if (enb) begin
        Delay_Synchronous_out1 <= DataIn;

When you disable this parameter, HDL Coder generates the global reset logic in the HDL code. This Verilog code snippet shows the reset logic generated for the Delay block.

  always @(posedge clk or posedge reset)
    begin : Delay_Synchronous_process
      if (reset == 1'b1) begin
        Delay_Synchronous_out1 <= 1'b0;
      else begin
        if (enb) begin
          Delay_Synchronous_out1 <= DataIn;


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to minimize global reset signals when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.


Recommended Settings

No recommended settings.

Programmatic Use

Parameter: MinimizeGlobalResets
Type: character vector
Value: 'on' | 'off'
Default: 'off'


Sometimes, when you select Minimize global resets, HDL Coder generates the reset logic, if you have:

  • Blocks with state that have a nonzero initial value, such as a Delay block with non-zero Initial Condition.

  • Enumerated data types for blocks with state.

  • Subsystem blocks with BlackBox HDL architecture where you request a reset signal.

  • Multirate models with Timing controller architecture set to default.

    If you set Timing controller architecture to resettable, HDL Coder generates a reset port for the timing controller. If you set Minimize global reset signals to 'on', the code generator removes this reset port.

  • Truth Table

  • Chart

  • MATLAB Function block

Version History

Introduced in R2017a