Main Content

Enable prefix

Base name as character vector

Model Configuration Pane: Global Settings / General


Specify the base name as a character vector for internal clock enables and other flow control signals in generated code.


'enb' (default) | character vector

Default: 'enb'

Where only a single clock enable is generated, Enable prefix specifies the signal name for the internal clock enable signal.

In some cases, the code generator can generate multiple clock enable signals. For example, if you specify a cascade block implementation for certain blocks, multiple clock enable signals are generated. In such cases, Enable prefix specifies a base signal name for the first clock enable that is generated. For other clock enable signals, numeric tags are appended to Enable prefix to form unique signal names. For example, the following code fragment illustrates two clock enables that were generated when Enable prefix was set to 'test_clk_enable':

COMPONENT mysys_tc
    PORT( clk                   :   IN    std_logic;
          reset                 :   IN    std_logic;
          clk_enable            :   IN    std_logic;
          test_clk_enable       :   OUT   std_logic;
          test_clk_enable_5_1_0 :   OUT   std_logic


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.


Recommended Settings

No recommended settings.

Programmatic Use

Parameter: EnablePrefix
Type: character vector
Default: 'enb'

Version History

Introduced in R2012a