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Verilog or SystemVerilog timescale specification

Timescale to use in generated Verilog or SystemVerilog code

Model Configuration Pane: Global Settings / Coding style


Specify the timescale that you want to use in the generated Verilog or SystemVerilog code.


This option is enabled when:

  • The target language (specified by the Language option) is Verilog or SystemVerilog.

  • The Use Verilog or SystemVerilog `timescale directives option is enabled.


`timescale 1 ns/1 ns (default) | character vector

Default: `timescale 1 ns/1 ns

HDL Coder™ applies this option to the timescale directive in the generated Verilog or SystemVerilog code. You can customize the default timescale and specify a valid, compilable timescale directive. The Verilog and SystemVerilog languages uses this directive to determine the time units and the precision for calculating delay values.

By default, both the time units and precision are 1ns. For example, if you customized the timescale to `timescale 1 ns/1 ps, a delay unit becomes 1ns and the value is precise to the nearest 1 ps.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: Timescale
Type: character vector
Value: A character vector that is a valid timescale value
Default: `timescale 1 ns/1 ns

Version History

Introduced in R2012a