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Package postfix

Text to append to model or subsystem name

Model Configuration Pane: Global Settings / General


Specify a text as a character vector to append to the model or subsystem name to form name of a package file.


  • This option is enabled when the target language (specified by the Language option) is VHDL® or SystemVerilog.

  • This option is enabled when the target language (specified by the Language option) is Verilog®, and the Multi-file test bench option is selected.

  • This option is ignored, when the HDL Coding Standard is set to Industry.


_pkg (default) | character vector

Default: _pkg

HDL Coder™ applies this option only if a package file is required for the design.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.


Recommended Settings

No recommended settings.

Programmatic Use

Parameter: PackagePostfix
Type: character vector
Value: A character vector that is legal in a VHDL package file name
Default: '_pkg'

Version History

Introduced in R2012a