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Initialize all RAM blocks

Generate initial signal value for RAM blocks

Model Configuration Pane: HDL Code Generation / Global Settings / Coding style

Description

The Initialize all RAM blocks parameter enables or disables the generation of initial signal value for RAM blocks. This setting is ignored if you specify a nonzero initial value for the RAM block by using the Specify the RAM initial value block parameter.

Settings

on (default) | off
on

Generate initial values of '0' for both the RAM signal and the output temporary signal of all RAM blocks.

off

Do not generate initial values for either the RAM signal or the output temporary signal of the RAM blocks.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

This parameter applies to these RAM blocks in the HDL Coder > HDL RAMs block library in the Simulink Library Browser:

  • Dual Port RAM

  • Dual Port RAM System

  • Dual Rate Dual Port RAM

  • HDL FIFO

  • Simple Dual Port RAM

  • Simple Dual Port RAM System

  • Simple Tri Port RAM System

  • Single Port RAM

  • Single Port RAM System

  • True Dual Port RAM System

Programmatic Use

Parameter: InitializeBlockRAM
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2012a

See Also

Functions

Topics