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Reset length (in clock cycles)

Define length of time (in clock cycles) during which reset is asserted

Model Configuration Pane: Test Bench


Define length of time (in clock cycles) during which reset is asserted.


This parameter is enabled when Force reset is selected.


2 (default)

The Reset length (in clock cycles) property defines the number of clock cycles during which reset is asserted. Reset length (in clock cycles) must be an integer greater than or equal to 0. The following figure illustrates the default case, in which the reset signal (active-high) is asserted for 2 clock cycles.


To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
                'Resetlength', 4)
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'Resetlength', 4)

Recommended Settings

No recommendations.

Programmatic Use

Parameter: Resetlength
Type: integer
Default: 2

Version History

Introduced in R2012a