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HDL test bench

Enable or disable HDL test bench generation

Model Configuration Pane: Test Bench


Enable or disable HDL test bench generation.


Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

This check box enables the options in the Configuration section of the Test Bench pane. Select a Simulation tool to generate scripts to build and run the test bench.


On (default) | Off

Enable generation of HDL test bench code. The code generator creates a HDL test bench by running a Simulink® simulation to capture input vectors and expected output data for your DUT.

This test bench is the default test bench that HDL Coder™ generates for your model. If you have not already generated code for your model, running HDL test bench generation also generates code for your DUT.

Specify your HDL simulator in the Simulation tool menu. HDL Coder generates build-and-run scripts for the simulator that you specify.


Suppress generation of HDL test bench code. You can use this option when you use an alternate test bench.


To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, to generate a HDL test bench for the sfir_fixed/symmetric_fir Subsystem, pass the DUT as an argument to the makehdltb function.


Recommended Settings

No recommendations.

Programmatic Use

Parameter: GenerateHDLTestBench
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2012a