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Generate HDL code

Enable or disable HDL code generation for model or Subsystem

Model Configuration Pane: Global Settings / Advanced


Enable or disable HDL code generation for the model or Subsystem. To specify the Subsystem that you want to generate HDL code for, use the Generate HDL for parameter. Then, click the Generate button in the HDL Code Generation pane. By default, the HDL code is generated in VHDL language and put into the hdlsrc folder.


on (default) | off

Default: On


Select this setting to generate HDL code.


When you clear this setting, you cannot generate HDL code for the model.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

By default, the GenerateHDLCode property is selected. To generate code, use the makehdl function. For example, this command generates HDL code for the symmetric_fir subsystem inside the sfir_fixed model.


Recommended Settings

No recommended settings.

Programmatic Use

Parameter: GenerateHDLCode
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2012a