Workflows in HDL Workflow Advisor

The HDL Workflow Advisor offers various workflows to check your algorithm for HDL compatibility, generate HDL code, verify the code, and then deploy the code to your target platform.

You can run the Workflow Advisor for your MATLAB^® algorithm or Simulink^® model. Before you deploy the code to a target hardware platform, install the synthesis tool and specify the path to that synthesis tool by using the hdlsetuptoolpath function. See Tool Setup.

HDL Workflow Advisor is not available in Simulink Online™.

Set Up HDL Workflow Advisor in MATLAB

Before you specify the target workflow, when you run the Workflow Advisor from MATLAB, specify the design and test bench files, define the input types, and run fixed-point conversion.

To specify the target workflow for code generation:

On the MATLAB toolstrip, from the Apps tab, select the HDL Coder app.
Select the MATLAB design and test bench files and click the Workflow Advisor button.
In the HDL Workflow Advisor, select Code Generation Workflow as MATLAB to HDL or MATLAB to SystemC.
In the Select Code Generation Target task, select the Workflow for code generation.

Note

The steps after code generation workflow selection change depending on your target workflow.

Set Up HDL Workflow Advisor in Simulink

When you run the Workflow Advisor from your Simulink model, irrespective of the target workflow, you run the steps to prepare the model for HDL code generation, and then generate code.

Open the Simulink model for which you want to run the workflow.

On the Simulink toolstrip, from the Apps tab, select the HDL Coder app.
On the HDL Code tab, click the Workflow Advisor button.
In the HDL Workflow Advisor, on the Set Target Device and Synthesis Tool task, select the Target workflow.

The steps in the Workflow Advisor change depending on the Target workflow, Target platform, and Synthesis tool.

Generic ASIC/FPGA

Generate HDL code from your Simulink model or MATLAB algorithm, verify the HDL code, and deploy the code to a generic ASIC or FPGA device.

By using this workflow, you can:

Generate HDL code for your fixed-point MATLAB algorithm or your HDL-compatible Simulink model.
Generate an HDL test bench and cosimulation test bench (requires HDL Verifier™), and scripts to build and run the code and test bench. You can also generate a SystemVerilog DPI test benches and code coverage when running the Simulink HDL Workflow Advisor (requires HDL Verifier).
Perform FPGA synthesis and timing analysis and rapidly prototype your design on generic FPGA platforms through integration with third-party synthesis tools.
Back-annotate the model with critical path information and other information obtained during synthesis, and then optimize your design for area and speed.
Note
If you select Intel Quartus Pro or Microchip Libero SoC as the Synthesis tool, the Annotate Model with Synthesis Result task is not available. To see the critical path, run the workflow to synthesis, and then open the timing reports.

To learn more, see:

IP Core Generation

Generate RTL code and a custom HDL IP core from your Simulink model or MATLAB algorithm. Before you run the workflow, partition your design into components that run on software and components that run on hardware. See Hardware-Software Co-Design Workflow for SoC Platforms.

The IP core is a shareable and reusable HDL component that consists of IP core definition files, HDL code generated for your algorithm, C header file with the register address map, and the IP core report. See:

Use this workflow to:

Generate a generic board-independent Xilinx^® or Intel^® HDL IP core.
Integrate the IP core into a reference design to target standalone FPGA boards or SoC platforms with Xilinx Vivado^® IP integrator or Intel Qsys.
Communicate with the generated HDL IP core by using embedded ARM processor or, from MATLAB, by using the HDL Verifier AXI Manager. See Set Up AXI Manager (HDL Verifier).

You can integrate the HDL IP core into HDL Coder™ provided reference designs such as the default system reference design or into a reference design that you created. To learn more, see:

Simulink Real-Time FPGA I/O

Generate HDL code from your Simulink model and deploy the code onto Speedgoat^® FPGA I/O modules. This workflow requires Xilinx Vivado and uses the IP Core Generation workflow infrastructure, as mentioned in Simulink Real-Time FPGA I/O: Speedgoat Target Computer.

To run the Simulink Real-Time FPGA I/O workflow, install the Speedgoat I/O Blockset and the Speedgoat HDL Coder Integration Packages. After you install the integration packages, you can choose the Target platform, and then run the workflow to:

Generate a reusable and shareable IP core.
Integrate the IP core into the Speedgoat reference design.
Generate an FPGA bitstream and download the bitstream to the target hardware.
Generate a Simulink Real-Time™ model. The model is an interface subsystem model that contains the blocks to program the FPGA and communicate with the board during real-time execution.

For more information, see IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules.

FPGA-in-the-Loop

Test your Simulink model or MATLAB algorithm on a target FPGA. This workflow requires HDL Verifier.

Use this workflow to:

Choose boards from the FPGA Board Manager that are FIL Enabled or create your own custom boards for verification. See FPGA Board Customization (HDL Verifier).
Generate HDL code for your fixed-point MATLAB algorithm or your HDL-compatible Simulink model.
Perform FPGA implementation and connect to the target FPGA board by using Ethernet, JTAG, or PCI Express for FIL simulation.

To learn more, see:

FIL Simulation with HDL Workflow Advisor for Simulink (HDL Verifier)
FIL Simulation with HDL Workflow Advisor for MATLAB (HDL Verifier)