Custom IP Core Report

R2026b

You generate an HTML custom IP core report by default when you generate a custom IP core. The report describes the behavior and contents of the generated custom IP core.

Summary

The Summary section shows your coder settings when you generated the custom IP core.

The following figure is an example of a Summary section.

Summary table listing IP core settings including name, version, target platform, target tool, and generation date

Target Interface Configuration

The Target Interface Configuration section shows how your DUT ports map to the target hardware interface and the processor/FPGA synchronization mode.

The following figure is an example of a Target Interface Configuration section.

Target interface table mapping DUT port names, types, and data types to AXI4 target platform interfaces with bit range addresses

To learn more about processor/FPGA synchronization modes, see Processor and FPGA Synchronization.

To learn more about target platform interfaces, see Custom IP Core Generation.

Register Address Mapping

The Register Address Mapping section shows the address offsets for AXI4-Lite bus accessible registers in your custom IP core, and the name of the C header file that contains the same address offsets.

The following figure is an example of a Register Address Mapping section.

Register address mapping table listing register names, hexadecimal address offsets, and descriptions for AXI4-Lite accessible registers

Bit Packing Order

The Bit Packing Order section gives a high-level overview of the data packing order for vector inputs and outputs for Internal IO, External IO, and External port interfaces. This section only appears when the port width for Internal IO, External IO, and External ports are set to greater than 128 bits wide.

This image is an example of the Bit packing Order section:

Bit packing and unpacking order for vector input and output signals, showing 128-bit segments mapped to DUT ports

IP Core User Guide

The IP Core User Guide section gives a high-level overview of the system architecture, describes the processor and FPGA synchronization mode, and gives instructions for integrating the IP core in your embedded system integration environment.

The following figure is an example of an IP Core User Guide system architecture description.

System architecture showing a processing system connected via AXI4-Lite to the IP core, which contains registers and the MATLAB/Simulink algorithm with external ports

When your design under test (DUT) contains any register, HDL Coder™ add this section to the IP core generation report:

Text describing the logic added for address decoder pipelining and a timing diagram explaining the added delay for each register.

The following figure is an example of a processor/FPGA synchronization description.

Timing diagram showing Free running synchronization mode with independent processor read/write and FPGA hardware execution

If you use vector data signals at the DUT interface, the IP core report displays this section that shows how the code generator synchronizes vector data across the AXI4 interface.

Vector data read/write with strobe synchronization, showing data and strobe registers for AXI4-Lite write and read operations

The following figure is an example of instructions for integrating the IP core into your embedded system integration environment on the Xilinx^® platform. If you are targeting an Altera^® platform, the report displays similar instructions for integrating the IP core into the Altera Qsys environment.

EDK Environment Integration instructions listing seven steps to add the IP core to a Xilinx EDK environment

IP Core File List

The IP Core File List section lists the files and file folders that comprise your custom IP core.

The following figure is an example of an IP core file list.

IP Core File List showing links to definition files, IP core report, HDL source files, and C header file

Frame-to-Sample Mode

When you enable the frame-to-sample optimization, the IP core report includes a Frame-to-Sample Mode section, which includes the Frame-to-Sample Mode section, which includes information such as high-level overviews of the frame-to-sample optimization, the generated code, and a summary of how the data is packed and streamed.

This image shows the section of the Frame-to-Sample Mode section, which includes an overview of the theory of operation for the frame-to-sample optimized IP core and a summary of how the large delays are offloaded to external memory.

Block diagram showing the HDL Coder IP Core: sample data enters from two AXI4‑Stream ports, passes through a Delay Manager and an Arbiter, then writes to external memory through an AXI4 Master connection and a memory controller.

When the design has implicit delays or design delays that exceed a specified threshold, the report includes the External Delay Mapping section, which details information about the external delay mapping such as delay ID, port name, AXI4-Master interfaces, and so on. This image shows the interface mapping table and in the table Port names with an * next to the name indicate that multiple signals are mapped to that port.

The External Delay Mapping table, listing the delay IDs and their port names, port types, data types, and AXI4 Master interface mappings for valid and ready signals.

This image shows the delay mapping and bandwidth estimation portion of the report. The bandwidth calculations include the updated multiple samples per cycle value.

Side-by-side comparison of performance summaries for 1 sample per cycle versus 4 samples per cycle, showing external delay sizes and base address offsets, and bandwidth tables indicating higher required AXI4 Master bandwidth and higher maximum frame rate for 4 samples per cycle.