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Entity conflict postfix

Text to resolve duplicate module names

Model Configuration Pane: Global Settings / General


Specify the text as a character vector to resolve duplicate VHDL® entity, Verilog® or SystemVerilog module names in generated code.


_block (default) | character vector

Default: _block

The specified postfix resolves duplicate VHDL entity, Verilog or SystemVerilog module names.

For example, if HDL Coder™ detects two entities with the name MyFilter, the coder names the first entity MyFilter and the second entity MyFilter_block.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.


Recommended Settings

No recommended settings.

Programmatic Use

Parameter: EntityConflictPostfix
Type: character vector
Value: A valid character vector in the target language
Default: '_block'

Version History

Introduced in R2012a

See Also