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Share Adders

Share adders with the resource sharing optimization

Model Configuration Pane: Optimization / Resource sharing


Enable this parameter to share adders with the resource sharing optimization. Resource sharing identifies Add or Sum blocks in your design that have two inputs and replaces them with a single Add or Sum block. This optimization saves area on the target FPGA device.


  • To share adders in your design, in the HDL Block Properties for the DUT Subsystem, specify the SharingFactor.

  • When you specify the Adder sharing minimum bitwidth, the code generator shares adders that have a bit width greater than or equal to the minimum bit width. The default minimum bit width for sharing adders is zero.


Off (default) | On

When resource sharing is enabled, this optimization shares adders with a bit width greater than or equal to the Adder sharing minimum bitwidth.


Do not share adders.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the ShareAdders setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.


Recommended Settings

No recommendations.

Programmatic Use

Parameter: ShareAdders
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Version History

Introduced in R2015a