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Cosimulation model

Enable or disable model generation

Model Configuration Pane: Test Bench


Enable or disable generation of a model including a HDL Cosimulation block. This option requires an HDL Verifier™ license. After you select this check box, specify your Simulation tool. You can select Mentor Graphics® ModelSim®, Cadence Incisive®, or Xilinx® Vivado® Simulator for cosimulation. Custom script settings are not supported with this test bench.

The code generator configures the generated HDL Cosimulation blocks to conform to the port and data type interface of the DUT selected for code generation. By connecting an HDL Cosimulation block to your model in place of the DUT, you can cosimulate your design with the desired simulator.

The coder appends the character vector that the CosimLibPostfix property specifies to the names of the generated HDL Cosimulation blocks.


Make sure that the system selected is the DUT. This option is disabled if you select the entire model.


Off (default) | On

Disable generation of a model including a HDL Cosimulation block.


Enable generation of a model including a HDL Cosimulation block.


To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can enable the GenerateCoSimModel property when you generate a testbench for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.


Recommended Settings

No recommendations.

Programmatic Use

Parameter: GenerateCoSimBlock | GenerateCoSimModel
Type: character vector
Generate CoSimBlock Values: 'on' | 'off'
Generate CoSimBlock Default: 'off'
Generate CoSimModel Values: 'ModelSim''Incisive''Vivado Simulator''None'
Generate CoSimModel Default: 'ModelSim'


Cosimulation model generation is not supported in MATLAB® to HDL workflow when the target language is SystemVerilog.

Version History

Introduced in R2012a