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Max number of I/O pins for FPGA deployment

Maximum number of I/O pins for target FPGA

Since R2022a

Model Configuration Pane: Global Settings / Ports


Specify the maximum number of I/O pins for your target FPGA.


5000 (default) | positive integer

Default: 5000

If the DUT pin count in the generated code exceeds the value of this parameter, HDL Coder™ generates the message type specified by the Check for DUT pin count exceeding I/O Threshold parameter in the HDL Code Generation Check Report.


To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: IOThreshold
Type: int32
Value: positive integer
Default: 5000

Version History

Introduced in R2022a