Configure Compilation, Simulation, Synthesis, and Lint Scripts

Configure the script file generation by using the EDA Tool Scripts pane. These options correspond to the properties described in Properties for Controlling Script Generation.

To view and set EDA Tool Scripts options:

Open the Configuration Parameters dialog box.
Select the HDL Code Generation > EDA Tool Scripts pane.
The Generate EDA scripts option controls the generation of script files. By default, this option is selected.
If you want to disable script generation, clear this check box and click Apply.
The list on the left of the EDA Tool Scripts pane lets you select from several categories of options. Select a category and set the options as desired. The categories are:
- Compilation script: Options related to customizing scripts for compilation of generated VHDL^®, Verilog^® or SystemVerilog code. For more information, see Compilation Script Options.
- Simulation script: Options related to customizing scripts for HDL simulators. For more information, see Simulation Script Options.
- Synthesis script: Options related to customizing scripts for synthesis tools. For more information, see Synthesis Script Options.
- Lint script: Options related to customizing scripts for HDL lint tools. For more information, see Lint Script Options.

Compilation Script Options

The following figure shows the Compilation script pane, with options set to their default values.

EDA Tools Compilation Script Options

The following table summarizes the Compilation script options.

Option and Default	Description
Name: Compile file postfix Default: `'_compile.do'`	Postfix appended to the DUT name or test bench name to form the script file name.
Name: Compile initialization Default: `'vlib %s\n'`	Format name passed to `fprintf` to write the `Init` section of the compilation script. The argument is the contents of the `VHDLLibraryName` property, which defaults to`'work'`. You can override the default `Init` `'vlib work\n'` by changing the value of `VHDLLibraryName`.
Name: Compile command for VHDL Default: `'vcom %s %s\n'`	Format name passed to `fprintf` to write the `Cmd` section of the compilation script for VHDL files. The two arguments are the contents of the `SimulatorFlags` property option and the filename of the current entity or module. To omit the flags, set `SimulatorFlags` to `''` (the default).
Name: Compile command for Verilog or SystemVerilog Default: `'vlog %s %s\n'`	Format name passed to `fprintf` to write the `Cmd` section of the compilation script for Verilog or SystemVerilog files. The two arguments are the contents of the `SimulatorFlags` property and the filename of the current entity or module. To omit the flags, set `SimulatorFlags` to `''` (the default).
Name: Compile termination Default:`''`	Format name passed to `fprintf` to write the termination portion of the compilation script.

Simulation Script Options

The following figure shows the Simulation script pane, with options set to their default values.

EDA Tools Simulation Script Options

The following table summarizes the Simulation script options.

Option and Default	Description
Name: Simulation file postfix Default: `'_sim.do'`	Postfix appended to the model name or test bench name to form the simulation script file name.
Simulation initialization Default: `['onbreak resume\nonerror resume\n']`	Format name passed to `fprintf` to write the initialization section of the simulation script.
Simulation command Default: `'vsim -voptargs=+acc %s.%s\n'`	Format name passed to `fprintf` to write the simulation command. If your `TargetLanguage` is `'VHDL'`, the first implicit argument is the value of `VHDLLibraryName`. If your `TargetLanguage` is `'Verilog'`or `'SystemVerilog'`, the first implicit argument is `'work'`. The second implicit argument is the top-level module or entity name.
Simulation waveform viewing command Default: `'add wave sim:%s\n'`	Format name passed to `fprintf` to write the simulation script waveform viewing command. The top-level module or entity signal names are implicit arguments.
Simulation termination Default: `'run -all\n'`	Format name passed to `fprintf` to write the `Term` portion of the simulation script.
Simulator flags Default: `<empty>`	Specify options that are specific to your application and the simulator you are using. For example, if you use the 1076-1993 VHDL compiler, specify the flag `-93`. The coder adds the flags you specify with this option to the compilation command in the generated EDA tool scripts.

Synthesis Script Options

The following figure shows the Synthesis script pane, with options set to their default values. The Choose synthesis tool property defaults to None, which disables generation of a synthesis script.

EDA Tools Synthesis Script Options

To enable synthesis script generation, select a synthesis tool from the Choose synthesis tool menu.

When you select a synthesis tool, HDL Coder™:

Enables synthesis script generation.
Enters a file name postfix (specific to the chosen synthesis tool) into the Synthesis file postfix field.
Enters strings (specific to the chosen synthesis tool) into the initialization, command, and termination fields.

The following figure shows the default option values entered for the Mentor Graphics^® Precision tool.

Synthesis Script for Mentor Graphics Precision tool

The following table summarizes the Synthesis script options.

Option Name Description

Choose synthesis tool

None (default): do not generate a synthesis script

Xilinx ISE: generate a synthesis script for Xilinx^® ISE

Microchip Libero: generate a synthesis script for Microchip Libero

Mentor Graphics Precision: generate a synthesis script for Mentor Graphics Precision

Altera Quartus II: generate a synthesis script for Altera^® Quartus II

Synopsys Synplify Pro: generate a synthesis script for Synopsys^® Synplify Pro^®

Xilinx Vivado: generate a synthesis script for Xilinx Vivado^®

Custom: generate a custom synthesis script

Synthesis file postfix

Your choice of synthesis tool sets the postfix for generated synthesis file names to one of the following:

_ise.tcl

_libero.tcl

_precision.tcl

_quartus.tcl

_synplify.tcl

_vivado.tcl

_custom.tcl

Synthesis initialization

Format name passed to fprintf to write the Init section of the synthesis script. The default string is a synthesis project creation command. The implicit argument is the top-level module or entity name.

The content of the string is specific to the selected synthesis tool.

Synthesis command

Format name passed to fprintf to write the Cmd section of the synthesis script. The implicit argument is the file name of the entity or module.

The content of the string is specific to the selected synthesis tool.

Synthesis termination

Format name passed to fprintf to write the Term section of the synthesis script.

The content of the string is specific to the selected synthesis tool.

Lint Script Options

The following figure shows the Lint script pane, with options set to their default values.

EDA Tool Lint Script pane

The following table summarizes the Lint script options.

Option	Description
Choose HDL lint tool	Enable or disable generation of an HDL lint script, and select the HDL lint tool for which HDL Coder generates a script.
Lint initialization	Enter an initialization text for your HDL lint script.
Lint command	Enter the command for your HDL lint script.
Lint termination	Enter a termination character vector for your HDL lint script.

To enable lint script generation, select a HDL lint tool from the Choose HDL lint tool menu.

When you select the HDL lint tool, HDL Coder:

Enables lint script generation.
Enters strings (specific to the chosen HDL lint tool) into the initialization, command, and termination fields.

You can also generate the custom lint script. Select Custom from the Choose HDL lint tool and enter strings into the initialization, command, and termination fields.

For more information, see Generate HDL Lint Tool Script.