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Customize Black Box or HDL Cosimulation Interface

You can customize port names and set attributes of the external component when you generate an interface from the following blocks:

  • Model with black box implementation

  • Subsystem with black box implementation

  • HDL Cosimulation

Interface Parameters

Open the HDL Block Properties dialog box to see the interface generation parameters.

The following table summarizes the names, value settings, and purpose of the interface generation parameters.

Note

You cannot specify clock, reset, and clock enable signals explicitly in your Simulink® model by using the AddClockEnablePort, AddClockPort, and AddResetPort parameters. Instead, use these parameters to add a clock, reset, or clock enable port in the generated HDL code.

Parameter NameValuesDescription
AddClockEnablePort

on | off

Default: on

If on, add a clock enable input port to the interface generated for the block. The name of the port is specified by ClockEnableInputPort.
AddClockPort

on | off

Default: on

If on, add a clock input port to the interface generated for the block. The name of the port is specified by ClockInputPort.

If AddClockPort is off, then AddClockEnablePort and AddResetPort is considered as off.

AddResetPort

on | off

Default: on

If on, add a reset input port to the interface generated for the block. The name of the port is specified by ResetInputPort.
AllowPipelineDistribution

on | off

Default: off

If on, allow HDL Coder™ to move registers across the block, from input to output or output to input.
ClockEnableInputPort

Default: clk_enable

Specifies HDL name for block's clock enable input port. To generate the clock enable input ports with the HDL names specified in this property, set AddClockEnablePort to on.

You can specify multiple clock enable names. The mapping of clock enables depends on input and output sample rates. The clock enable ports are mapped from fastest to slowest sample rate.

For example, if your model has two sample rates and you specify ["clken1" "clken2"] as the clock enable names to this property. The clken1 is mapped to the faster sample rate and clken2 is mapped to the slower rate.

When Clock inputs is Single, specify either one or N clock enable port names. Where N is number of sample rates. When Clock inputs is Multiple, specify N clock enable port names.

ClockInputPort

Default: clk

Specifies HDL name for block's clock input signal. To generate the clock input ports with the HDL name specified in this property, set AddClockPort to on.

You can specify multiple clock port names. The mapping of clock ports depends on input and output sample rates. The clock ports are mapped from fastest to slowest sample rate.

For example, if your model has two sample rates and you specify ["clk1" "clk2"] as the clock names to this property. The clk1 is mapped to the faster sample rate and clk2 is mapped to the slower rate.

When Clock inputs is Single, specify one clock input port name. When Clock inputs is Multiple, specify N clock input port names. Where N is number of sample rates.

ConstrainedOutputPipeline

Default: 0

Specifies the number of delays that you want the code generator to insert at the output of the interface by redistributing existing delays in your design.
EntityName

Default: Entity name string is derived from the block name, and modified when necessary to generate a legal VHDL® entity name.

Specifies VHDL entity, or Verilog® or SystemVerilog module name generated for the block.

GenericList

Pass a cell array variable that contains cell arrays each with two or three character arrays, or enter a cell array of cell arrays that each contain two or three character arrays. The character arrays represent the name, value, and optional data type of a VHDL generic, or Verilog or SystemVerilog parameter. The default data type is integer.

Default: none

Specifies a list of VHDL generic, or Verilog or SystemVerilog parameter name-value pairs, each with an optional data type specification, to pass to a subsystem with a BlackBox implementation.

For example, in the HDL Block Properties dialog box, enter {{'name','value','type'}}, or, if the data type is integer, enter {{'name','value'}}.

To set GenericList using hdlset_param, at the command line, enter:

hdlset_param (blockname,'GenericList','{{''name'',''value'',''type''}}');

If the data type is integer, at the command line, enter:

hdlset_param (blockname,'GenericList','{{''name'',''value''}}');. For more information, see Generate Black Box Interface for Subsystem.

ImplementationLatency

-1 | 0 | positive integer

Default: -1

Specifies the additional latency of the external component in time steps, relative to the Simulink block.

If 0 or greater, this value is used for delay balancing. Your inputs and outputs must operate at the same rate.

If -1, latency is unknown. This disables delay balancing.

For Black Box subsystem that has multiple sample rates, the product of ImplementationLatency and slowest output sample rate must be divisible by all the output sample rates.

InlineConfigurations
(VHDL only)

on | off

Default: If this parameter is unspecified, defaults to the value of the global InlineConfigurations property.

If off, suppress generation of a configuration for the block, and require a user-supplied external configuration.
InputPipeline

Default: 0

Specifies the number of input pipeline stages (pipeline depth) in the generated code.
OutputPipeline

Default: 0

Specifies the number of output pipeline stages (pipeline depth) in the generated code.
ResetInputPort

Default: reset

Specifies HDL name for block's reset input. To generate the reset input ports with the HDL name specified in this property, set AddResetPort to on.

You can specify multiple reset port names. The mapping of reset ports depends on input and output sample rates. The reset ports are mapped from fastest to slowest sample rate.

For example, if your model has two sample rates and you specify ["rst1" "rst2"] as the reset names to this property. The rst1 is mapped to the faster sample rate and rst2 is mapped to the slower rate.

When Clock inputs is Single, specify one reset input port name. When Clock inputs is Multiple, specify N reset input port names. Where N is number of sample rates.

VHDLArchitectureName
(VHDL only)

Default: rtl

Specifies RTL architecture name generated for the block. The architecture name is generated only if InlineConfigurations is on.
VHDLComponentLibrary
(VHDL only)

Default: work

Specifies the library from which to load the VHDL component.

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