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Implement Atan2 Block with Control Signals

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This example shows how to implement the control-signal based Atan2 block and use it to generate HDL code.

Open and Run Simulink Model

Specify the input data as a linear sweep through values in the range [-pi, pi]. You can change these values according to your requirements.

input_values = (-pi:.01/(2*pi):pi)';
RADIUS = 10.^(-2.5:.25:0);

Specify the word length for fixed-point data types and the latency for the model. The latency depends on the number of iterations.

WL_atan2 = 18; latency_atan2 = 14;

Map the input data to x- and y-coordinate values.

x_log = zeros(length(input_values)*length(RADIUS),1);
y_log = zeros(length(input_values)*length(RADIUS),1);
for outerindex = 0:length(RADIUS)-1
    for index = 1:length(input_values)
        input = input_values(index);  % access current value
        y = RADIUS(outerindex+1)*sin(input);               % compute y
        x = RADIUS(outerindex+1)*cos(input);               % compute x
        addr = outerindex*length(input_values)+index;
        y_log(addr) = y;
        x_log(addr) = x;
    end
end

Open the hdlcoder_atan2_control model and specify a stop time sufficient to process all the input combinations. The model has an Atan2 block that implements the four-quadrant arctangent operation using the CORDIC algorithm.

stoptime_atan2 = length(x_log)-1+latency_atan2;
close all
open_system('hdlcoder_atan2_control')
sim('hdlcoder_atan2_control')

This figure shows the output waveform when you simulate the model. The dataOut output is valid when validOut is 1.

Validate Simulink Output By Using Reference Output

To validate the output of the Simulink model, compare this output with a reference value. To obtain the reference value, use the atan2 MATLAB function. The maximum error value is significantly smaller than the output of the model.

comparison_plot_atan2(atan2(y_log,x_log),sim_final_theta(valid_out),3,'theta');

Maximum Error theta 7.233221e-03

Generate HDL Code for Atan2 Implementation

Check the HDL settings of the model by using the hdlsaveparams function.

hdlsaveparams('hdlcoder_atan2_control')

%% Set Model 'hdlcoder_atan2_control' HDL parameters
hdlset_param('hdlcoder_atan2_control', 'HDLSubsystem', 'hdlcoder_atan2_control/Atan2');
hdlset_param('hdlcoder_atan2_control', 'ResetType', 'Synchronous');
hdlset_param('hdlcoder_atan2_control', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('hdlcoder_atan2_control', 'SynthesisToolChipFamily', 'Virtex7');
hdlset_param('hdlcoder_atan2_control', 'SynthesisToolDeviceName', 'xc7v2000t');
hdlset_param('hdlcoder_atan2_control', 'SynthesisToolPackageName', 'fhg1761');
hdlset_param('hdlcoder_atan2_control', 'SynthesisToolSpeedValue', '-2');
hdlset_param('hdlcoder_atan2_control', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('hdlcoder_atan2_control', 'TargetFrequency', 500);

hdlset_param('hdlcoder_atan2_control/Atan2/Atan2', 'Architecture', 'Cordic');

hdlset_param('hdlcoder_atan2_control/Atan2/LumpLatency', 'Architecture', 'MATLAB Datapath');
% Set SubSystem HDL parameters
hdlset_param('hdlcoder_atan2_control/Atan2/LumpLatency', 'FlattenHierarchy', 'on');

hdlset_param('hdlcoder_atan2_control/Atan2/ValidLine', 'Architecture', 'MATLAB Datapath');
% Set SubSystem HDL parameters
hdlset_param('hdlcoder_atan2_control/Atan2/ValidLine', 'FlattenHierarchy', 'on');

To generate HDL code for the Atan2 block in the model, use the makehdl function.

makehdl('hdlcoder_atan2_control/Atan2')
close_system('hdlcoder_atan2_control')
close all;

### Working on the model <a href="matlab:open_system('hdlcoder_atan2_control')">hdlcoder_atan2_control</a>
### Generating HDL for <a href="matlab:open_system('hdlcoder_atan2_control/Atan2')">hdlcoder_atan2_control/Atan2</a>
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_atan2_control', { 'HDL Code Generation' } )">hdlcoder_atan2_control</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_atan2_control'.
### Begin compilation of the model 'hdlcoder_atan2_control'...
### Begin compilation of the model 'hdlcoder_atan2_control'...
### Working on the model 'hdlcoder_atan2_control'...
### Working on... <a href="matlab:configset.internal.open('hdlcoder_atan2_control', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_hdlcoder_atan2_control'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at <a href="matlab:open_system('hdl_prj/hdlsrc/hdlcoder_atan2_control/gm_hdlcoder_atan2_control.slx')">hdl_prj/hdlsrc/hdlcoder_atan2_control/gm_hdlcoder_atan2_control.slx</a>
### Begin VHDL Code Generation for 'hdlcoder_atan2_control'.
### Working on hdlcoder_atan2_control/Atan2/Atan2 as hdl_prj/hdlsrc/hdlcoder_atan2_control/Atan2_block.vhd.
### Working on hdlcoder_atan2_control/Atan2 as hdl_prj/hdlsrc/hdlcoder_atan2_control/Atan2.vhd.
### Code Generation for 'hdlcoder_atan2_control' completed.
### Generating HTML files for code generation report at <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc24b_2725827_3888224/tp6f091d34/hdlcoder-ex94659518/hdl_prj/hdlsrc/hdlcoder_atan2_control/html/hdlcoder_atan2_control_codegen_rpt.html')">hdlcoder_atan2_control_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc24b_2725827_3888224/tp6f091d34/hdlcoder-ex94659518/hdl_prj/hdlsrc/hdlcoder_atan2_control/Atan2_report.html
### HDL check for 'hdlcoder_atan2_control' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

Atan2 Block Synthesis Performance

This figure shows the Atan2 block synthesis performance on the Xilinx® Virtex® 7 and Intel® Stratix® V devices.