基本 HDL 算法

使用基本 Simulink^® 模块创建简单 HDL 设计

HDL Coder 模块库包含许多基本模块，您可将其添加到 Simulink 建模环境并开发 HDL 算法。这些模块包括输入源、输出信宿及执行基础到复杂数学和三角运算的模块。

要过滤 Simulink 库浏览器以仅显示 HDL 支持的模块，请输入 hdllib。本节列出的模块包括仅在 HDL Coder 库中可用的模块。Add 和 Product 等模块在库浏览器的 Simulink 库中提供。

有关过滤后的支持 HDL 代码生成的 Simulink 模块的列表，请参阅 Simulink 模块列表（HDL 代码生成）。

函数

hdllib Display blocks that are compatible with HDL code generation

检查

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模块级检查

Check for infinite and continuous sample time sources

Check for large matrix operations

模块

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逻辑和位运算

Bit Concat	Concatenates up to 128 input words into single output
Bit Reduce	AND, OR, or XOR bit reduction on all input signal bits to single bit
Bit Rotate	Rotate input signal by bit positions
Bit Shift	Logical or arithmetic shift of input signal
Bit Slice	Return field of consecutive bits from input signal
Bits to Word	Convert vector of bits to integer (自 R2023a 起)
Word to Bits	Converts real numbers to vector of bits (自 R2023a 起)

查找表

Sine HDL Optimized and Cosine HDL Optimized

Implement fixed-point sine and cosine wave by using lookup table approach optimized for HDL code generation

源

HDL Counter

Free-running or count-limited hardware counter

HDL 数学库

Atan2	Compute Atan2 operation using CORDIC approximation method and simulate with latency
Sin	Compute sine operation using CORDIC approximation method and simulate with latency
Cos	Compute cosine operation using CORDIC approximation method and simulate with latency
Cos+jSin	Compute `Cos+jSin` operation using CORDIC approximation method and simulate with latency
SinCos	Compute `SinCos` operation using CORDIC approximation method and simulate with latency
rSqrt	Compute reciprocal square-root operation and simulate with latency
Sqrt	Compute Sqrt operation and simulate with latency
Divide	Compute division operation and simulate with latency
Reciprocal	Compute reciprocal operation and simulate with latency

主题

基础建模

Model and Debug Test Point Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.
Generate DUT Ports for Tunable Parameters
Generate DUT ports for tunable parameters.
Generate HDL Code with Annotations or Comments
How to add annotations to generated HDL code using the DocBlock and model annotations.
Scalarization of Vector Ports in Generated VHDL Code
Flatten vector signals on entire model or at DUT level into a structure of scalar signals in generated VHDL or SystemVerilog code.
Simulate and Generate HDL Code for the Float Typecast Block
Use Float Typecast block to cast input to floating-point or fixed-point.

数据类型支持

Supported Data Types and Scope
MATLAB^® data type and scope support for HDL code generation.
Signal and Data Type Support
HDL code generation support for signal types and data types.

精选示例

Implement Control Signal-Based Mathematical Functions by Using HDL Coder

HDL Coder™ provides HDLMathLib blocks that have control signal-based fixed-point mathematical functions. The blocks have control signals that indicate whether the input and output data are valid. You can also simulate these blocks with latency.

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Implement Sqrt Block with Control Signals

Implement the control-signal based Square root block and use it to generate HDL code.

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Implement rSqrt Block with Control Signals

Implement the control-signal based reciprocal square root block and use it to generate HDL code.

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Implement Divide Block with Control Signals

Implement the control-signal based Divide block and use it to generate HDL code.

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Implement Reciprocal Block with Control Signals

Implement the control-signal based Reciprocal block and use it to generate HDL code.

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Implement Atan2 Block with Control Signals

Implement the control-signal based Atan2 block and use it to generate HDL code.

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Implement Sine and Cosine Block with Control Signals

Implement the control-signal based SinCos block and use it generate HDL code.

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Convert Input Vector of Bits to Integer

Use the Bits to Word block in a Simulink® Model that converts vector of bits to an unsigned integer. You also generate HDL code for the model.

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Convert Integer to Vector of Bits

Implement the Word to Bits block in a Simulink® Model that converts an integer to a vector of bits. You also generate HDL code for the model.

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