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Implement Divide Block with Control Signals

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This example shows how to implement the control-signal based Divide block and use it to generate HDL code.

Open and Run Simulink Model

Specify the input data as a linear sweep. You can change these values according to your requirements.

divisor_input = fi(1/2^17:1/2^17:1,0,18,17)';
dividend_input = fi((1/2^17 + 1/2^16):1/2^17:1,0,18,17)';
divisor_input_size = size(divisor_input);
dividend_input_size = size(dividend_input);
if(divisor_input_size(1) > dividend_input_size(1))
    data_size = dividend_input_size(1);
else
    data_size = divisor_input_size(1);
end
dividend_input = dividend_input(1:data_size,1);
divisor_input =  divisor_input(1:data_size,1);

Specify the word length for fixed-point datatypes and the latency for the model. For more information on the latency calculation, see Divide.

WL_divide = 18;  divide_latency = 39;

Open the hdlcoder_divide_shiftadd_control model and specify a stop time sufficient to process all the input combinations.

stoptime_divide = length(dividend_input)-1+divide_latency;
open_system('hdlcoder_divide_shiftadd_control')
sim('hdlcoder_divide_shiftadd_control')

The figure shows waveform when you simulate the above model. The dataOut output is valid when validOut is 1.

Validate Simulink Output By Using Reference Output

To validate the output of the Simulink model, compare this output with a reference value. Compute the reference output by using the divide function.

ref_divide = double(dividend_input)./double(divisor_input);

Use logical indexing to extract valid output.

implementation_divide = simulink_divide(valid_output);

Plot the comparison results by using the comparison_plot_divide function. The maximum error value is significantly smaller than the output of the model.

comparison_plot_divide(ref_divide,implementation_divide,11,'divide linear input');

Maximum Error divide linear input 1.525844e-05 
Maximum PctError divide linear input 1.525786e-03

Generate HDL Code for Divide Implementation

Check HDL settings of the model by using the hdlsaveparams function.

hdlsaveparams('hdlcoder_divide_shiftadd_control')

%% Set Model 'hdlcoder_divide_shiftadd_control' HDL parameters
hdlset_param('hdlcoder_divide_shiftadd_control', 'Backannotation', 'on');
hdlset_param('hdlcoder_divide_shiftadd_control', 'HDLSubsystem', 'hdlcoder_divide_shiftadd_control/Divide');
hdlset_param('hdlcoder_divide_shiftadd_control', 'ResetType', 'Synchronous');
hdlset_param('hdlcoder_divide_shiftadd_control', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('hdlcoder_divide_shiftadd_control', 'SynthesisToolChipFamily', 'Virtex7');
hdlset_param('hdlcoder_divide_shiftadd_control', 'SynthesisToolDeviceName', 'xc7v2000t');
hdlset_param('hdlcoder_divide_shiftadd_control', 'SynthesisToolPackageName', 'fhg1761');
hdlset_param('hdlcoder_divide_shiftadd_control', 'SynthesisToolSpeedValue', '-2');
hdlset_param('hdlcoder_divide_shiftadd_control', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('hdlcoder_divide_shiftadd_control', 'TargetFrequency', 500);
hdlset_param('hdlcoder_divide_shiftadd_control', 'Traceability', 'on');

% Set SubSystem HDL parameters
hdlset_param('hdlcoder_divide_shiftadd_control/Divide', 'FlattenHierarchy', 'on');

hdlset_param('hdlcoder_divide_shiftadd_control/Divide/Divide', 'Architecture', 'ShiftAdd');
% Set Product HDL parameters
hdlset_param('hdlcoder_divide_shiftadd_control/Divide/Divide', 'LatencyStrategy', 'Max');

hdlset_param('hdlcoder_divide_shiftadd_control/Divide/LumpLatency', 'Architecture', 'MATLAB Datapath');
% Set SubSystem HDL parameters
hdlset_param('hdlcoder_divide_shiftadd_control/Divide/LumpLatency', 'FlattenHierarchy', 'on');

hdlset_param('hdlcoder_divide_shiftadd_control/Divide/ValidLine', 'Architecture', 'MATLAB Datapath');
% Set SubSystem HDL parameters
hdlset_param('hdlcoder_divide_shiftadd_control/Divide/ValidLine', 'FlattenHierarchy', 'on');

To generate HDL code for the Divide block in the model, use makehdl function.

makehdl('hdlcoder_divide_shiftadd_control/Divide')
close_system('hdlcoder_divide_shiftadd_control')
close all;

### Working on the model <a href="matlab:open_system('hdlcoder_divide_shiftadd_control')">hdlcoder_divide_shiftadd_control</a>
### Generating HDL for <a href="matlab:open_system('hdlcoder_divide_shiftadd_control/Divide')">hdlcoder_divide_shiftadd_control/Divide</a>
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_divide_shiftadd_control', { 'HDL Code Generation' } )">hdlcoder_divide_shiftadd_control</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_divide_shiftadd_control'.
### Begin compilation of the model 'hdlcoder_divide_shiftadd_control'...
### Begin compilation of the model 'hdlcoder_divide_shiftadd_control'...
### Working on the model 'hdlcoder_divide_shiftadd_control'...
### Working on... <a href="matlab:configset.internal.open('hdlcoder_divide_shiftadd_control', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_hdlcoder_divide_shiftadd_control'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at <a href="matlab:open_system('hdl_prj/hdlsrc/hdlcoder_divide_shiftadd_control/gm_hdlcoder_divide_shiftadd_control.slx')">hdl_prj/hdlsrc/hdlcoder_divide_shiftadd_control/gm_hdlcoder_divide_shiftadd_control.slx</a>
### Begin VHDL Code Generation for 'hdlcoder_divide_shiftadd_control'.
### Working on... <a href="matlab:configset.internal.open('hdlcoder_divide_shiftadd_control', 'Traceability')">Traceability</a>
### Working on hdlcoder_divide_shiftadd_control/Divide/Divide as hdl_prj/hdlsrc/hdlcoder_divide_shiftadd_control/Divide_block.vhd.
### Working on hdlcoder_divide_shiftadd_control/Divide as hdl_prj/hdlsrc/hdlcoder_divide_shiftadd_control/Divide.vhd.
### Code Generation for 'hdlcoder_divide_shiftadd_control' completed.
### Generating HTML files for code generation report at <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc24b_2725827_3888224/tp6f091d34/hdlcoder-ex91732492/hdl_prj/hdlsrc/hdlcoder_divide_shiftadd_control/html/hdlcoder_divide_shiftadd_control_codegen_rpt.html')">hdlcoder_divide_shiftadd_control_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc24b_2725827_3888224/tp6f091d34/hdlcoder-ex91732492/hdl_prj/hdlsrc/hdlcoder_divide_shiftadd_control/Divide_report.html
### HDL check for 'hdlcoder_divide_shiftadd_control' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.

Divide Block Synthesis Performance

This figure shows the Divide block synthesis performance on the Xilinx® Virtex® 7 and Intel® Stratix® V devices.