主要内容

层次化设计与同步硬件行为

使用 State Control 模块创建子系统和层次化 HDL 设计

HDL Coder 模块库包含许多模块,您可将其添加到 Simulink® 建模环境并开发 HDL 算法。要进行大型设计建模,您可以将模型划分为若干子系统并创建层次化设计。为实现同步硬件行为并生成硬件友好的 HDL 代码,请在子系统内使用 State Control 模块。

要过滤 Simulink 库浏览器以仅显示 HDL 支持的模块,请输入 hdllib。本节列出的模块包括仅在 HDL Coder 库中可用的模块。Foreach SubsystemAtomic Subsystem 等模块在库浏览器的 Simulink 库中提供。

有关经过过滤的 HDL 代码生成支持的 Simulink 模块的列表,请参阅 Simulink 模块列表(HDL 代码生成)

函数

hdllibDisplay blocks that are compatible with HDL code generation

模块

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Unit Delay Enabled SynchronousDelay input signal by one sample period when external Enable signal is true
Unit Delay Resettable SynchronousDelay input signal by one sample period when external Reset signal is false
Unit Delay Enabled Resettable SynchronousDelay input signal by one sample period when external Enable signal is true and external Reset signal is false
Tapped Delay Enabled SynchronousDelay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true (自 R2023a 起)
Tapped Delay Resettable SynchronousDelay scalar signal multiple sample periods and output all delayed versions when external Reset signal is false (自 R2023a 起)
Tapped Delay Enabled Resettable SynchronousDelay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false (自 R2023a 起)
Enabled DelayDelay input signal by fixed or variable sample periods when external enable signal is true (自 R2024b 起)
Enabled Resettable DelayDelay input signal by fixed or variable sample periods when external Enable signal is true and external Reset signal is false (自 R2024b 起)
State ControlSpecify synchronous reset and enable behavior for blocks with state
Synchronous SubsystemRepresent subsystem that has synchronous reset and enable behavior
Enabled Synchronous SubsystemRepresent enabled subsystem that has synchronous reset and enable behavior
Resettable Synchronous SubsystemRepresent resettable subsystem that has synchronous reset and enable behavior

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