层次化设计与同步硬件行为

使用 State Control 模块创建子系统和层次化 HDL 设计

HDL Coder 模块库包含许多模块，您可将其添加到 Simulink^® 建模环境并开发 HDL 算法。要进行大型设计建模，您可以将模型划分为若干子系统并创建层次化设计。为实现同步硬件行为并生成硬件友好的 HDL 代码，请在子系统内使用 State Control 模块。

要过滤 Simulink 库浏览器以仅显示 HDL 支持的模块，请输入 hdllib。本节列出的模块包括仅在 HDL Coder 库中可用的模块。Foreach Subsystem 和 Atomic Subsystem 等模块在库浏览器的 Simulink 库中提供。

有关经过过滤的 HDL 代码生成支持的 Simulink 模块的列表，请参阅 Simulink 模块列表（HDL 代码生成）。

函数

hdllib Display blocks that are compatible with HDL code generation

检查

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子系统级检查

Check for obsolete Unit Delay Enabled/Resettable Blocks

Check for invalid top level subsystem

模块

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离散

Unit Delay Enabled Synchronous	Delay input signal by one sample period when external Enable signal is true
Unit Delay Resettable Synchronous	Delay input signal by one sample period when external Reset signal is false
Unit Delay Enabled Resettable Synchronous	Delay input signal by one sample period when external Enable signal is true and external Reset signal is false
Tapped Delay Enabled Synchronous	Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true (自 R2023a 起)
Tapped Delay Resettable Synchronous	Delay scalar signal multiple sample periods and output all delayed versions when external Reset signal is false (自 R2023a 起)
Tapped Delay Enabled Resettable Synchronous	Delay scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false (自 R2023a 起)
Enabled Delay	Delay input signal by fixed or variable sample periods when external enable signal is true (自 R2024b 起)
Enabled Resettable Delay	Delay input signal by fixed or variable sample periods when external Enable signal is true and external Reset signal is false (自 R2024b 起)

HDL 子系统

State Control	Specify synchronous reset and enable behavior for blocks with state
Synchronous Subsystem	Represent subsystem that has synchronous reset and enable behavior
Enabled Synchronous Subsystem	Represent enabled subsystem that has synchronous reset and enable behavior
Resettable Synchronous Subsystem	Represent resettable subsystem that has synchronous reset and enable behavior

主题

Synchronous Subsystem Behavior with the State Control Block
Description of a State Control Block and how it generates cleaner HDL code.
Generating HDL Code for Subsystems with Array of Buses
Generate HDL code for subsystems that use array of buses in the design.
Generate Reusable Code for Subsystems
Generate shared code for identical subsystems or subsystems identical except for their mask parameter values.
Generate Parameterized Code for Referenced Models
Generate VHDL^® generic, Verilog^® or SystemVerilog parameter for model arguments in a model reference.
Generate HDL Code for Blocks Inside For Each Subsystem
An example that shows how to model and generate HDL code for blocks inside a For Each Subsystem.
Model Referencing for HDL Code Generation
Generate HDL code for referenced models.
Generate Incremental HDL Code for Referenced Models
When incremental code is generated for referenced models.
Set Configuration Parameters for HDL Code Generation of Model Hierarchies
Satisfy model reference hierarchy requirements to enable HDL code generation.
Generate HDL Code with Record or Structure Types for Bus Signals
Generate VHDL code with record or structure types for bus signals at different subsystem-level interfaces.

精选示例

Using the State Control Block to Generate More Efficient Code with HDL Coder

Use the State Control block to generate hardware-friendly HDL code using HDL Coder™.

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Resettable Subsystem Support in HDL Coder

Use Resettable Subsystems in HDL Coder™.

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Using ForEach Subsystems in HDL Coder

Use a For Each Subsystem to implement a streaming square root algorithm by cascading identical CORDIC iterations. You can then generate code for the algorithm by using HDL Coder™.

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Field-Oriented Control of a Permanent Magnet Synchronous Machine

Generate HDL code for a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM).

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Simulate and Generate HDL Code for Tapped Delay Enabled Resettable Synchronous Block

Implement the Tapped Delay Enabled Resettable Synchronous block in a Simulink® model that a delays scalar signal multiple sample periods and output all delayed versions when external Enable signal is true and external Reset signal is false. You also generate HDL code for the model.

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Generate HDL Code When Using Vector Data Type Inputs with Enable Signal Port

Generate HDL code for the Unit Delay Enabled Synchronous block when using vector data inputs with Enable signal port.

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Simulate and Generate HDL Code for Unit Delay Resettable Synchronous Block

Simulate and generate HDL code for the Unit Delay Resettable Synchronous block.

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