Unit Delay Enabled Resettable Synchronous

Delay input signal by one sample period when external Enable signal is true and external Reset signal is false

Libraries:
HDL Coder / Discrete

Description

The Unit Delay Enabled Resettable Synchronous block combines the functionality of the Unit Delay Enabled Synchronous block and the Unit Delay Resettable Synchronous block.

The Unit Delay Enabled Resettable Synchronous block delays the input signal u by one sample period when the external Enable signal is true and when the external Reset signal is false. When the Enable signal is false, the state and output signal hold the previous value. When the Reset signal is true, the state and output signal take the value of the Initial condition parameter. The Enable and Reset signals are true when E and R are nonzero and false when E and R equal zero.

The Unit Delay Enabled Synchronous block implementation consists of a Synchronous Subsystem that contains an Enabled Delay block with a Delay length of one and a State Control block in Synchronous mode. When you use this block in your model and have HDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware resources due to the Synchronous behavior of the State Control block.

Limitations

The block does not support vector inputs on the Reset and Enable ports.
You cannot use the block inside Enabled Subsystem, Triggered Subsystem, or Resettable Subsystem blocks that use Classic semantics. The Subsystem must use Synchronous semantics.

Ports

Input

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u — Input signal
`Scalar` | `Vector` | `Matrix` | `Array` | `Bus`

The Unit Delay Enabled Resettable Synchronous block accepts the input signal of the data types listed below. For more information, see Data Types Supported by Simulink.

Input

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E — Enable signal
`Scalar`

The Unit Delay Enabled Synchronous block accepts the Enable signal of the data types listed below. For more information, see Data Types Supported by Simulink.

R — Reset signal
`Scalar`

The Unit Delay Resettable Synchronous block accepts the Reset signal of the data types listed below. For more information, see Data Types Supported by Simulink.

Output

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y — Output signal
`Scalar` | `Vector` | `Matrix` | `Array` | `Bus`

Output data type matches input.

Parameters

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Initial condition — Initial output of simulation
0.0 (default) | `Scalar` | `Vector` | `Matrix` | `Array` | `Bus`

The Initial condition can take a scalar input or use the same data type as the input signal. You cannot run the simulation with NaN or Inf as the Initial condition.

Programmatic Use

Block parameter: InitialCondition

Type: character vector

Value: '0' | '[n]' |

'[m
                                    n]'

Default: '0'

Sample time — Time interval between samples
-1 (default) | `Scalar` | `Vector`

The Sample time must be a real double scalar that specifies the period or a real double vector of length two that specifies the period and offset. The period and offset must be finite and non-negative with offset less than the period.

Programmatic Use

Block parameter: SampleTime

Type: character vector

Value: '-1' | '[n]' |

'[m
                                    n]'

Default: '-1'

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.
ResetType	Suppress reset logic generation. The default is `default`, which generates reset logic. See also ResetType.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

HDL code generation supports only boolean datatype at the Reset and Enable ports.

Version History

Introduced in R2017b

Unit Delay Enabled Resettable Synchronous

Description

Limitations

Ports

Input

u — Input signal Scalar | Vector | Matrix | Array | Bus

Input

E — Enable signal Scalar

R — Reset signal Scalar

Output

y — Output signal Scalar | Vector | Matrix | Array | Bus

Parameters

Initial condition — Initial output of simulation 0.0 (default) | Scalar | Vector | Matrix | Array | Bus

Programmatic Use

Sample time — Time interval between samples -1 (default) | Scalar | Vector

Programmatic Use

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

u — Input signal
`Scalar` | `Vector` | `Matrix` | `Array` | `Bus`

E — Enable signal
`Scalar`

R — Reset signal
`Scalar`

y — Output signal
`Scalar` | `Vector` | `Matrix` | `Array` | `Bus`

Initial condition — Initial output of simulation
0.0 (default) | `Scalar` | `Vector` | `Matrix` | `Array` | `Bus`

Sample time — Time interval between samples
-1 (default) | `Scalar` | `Vector`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.