Actual data type or capability support depends on block implementation.
HDL Coder™ provides additional configuration options that
affect HDL implementation and synthesized logic.
HDL Architecture| Architecture | Description |
|---|
Module (default) | Generate code for the subsystem and the blocks within the subsystem. |
BlackBox | Generate a black box interface. The generated HDL code
includes only the input/output port definitions for the subsystem.
Therefore, you can use a subsystem in your model to generate an interface
to existing, manually written HDL code. The black-box
interface generation for subsystems is similar to the Model block
interface generation without the clock signals. |
No HDL
| Remove the subsystem from the generated code. You can
use the subsystem in simulation, however, treat it as a “no-op”
in the HDL code. |
HDL Block Properties| General |
|---|
| AdaptivePipelining | Automatic pipeline insertion based on the synthesis tool, target frequency, and
multiplier word-lengths. The default is inherit. See also
AdaptivePipelining.
|
| ClockRatePipelining | Insert pipeline registers at a faster clock rate instead of the slower data rate. The
default is inherit. See also ClockRatePipelining.
|
| ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
0. For more details, see ConstrainedOutputPipeline.
|
| DistributedPipelining | Pipeline register distribution,
or register retiming. The default is inherit. See
also DistributedPipelining.
|
| DSPStyle | Synthesis attributes for multiplier mapping. The default is none.
See also DSPStyle.
|
| FlattenHierarchy | Remove subsystem hierarchy from generated HDL code. The default
is inherit. See also FlattenHierarchy.
|
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see InputPipeline.
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see OutputPipeline.
|
| SharingFactor | Number of functionally equivalent resources to map to a single
shared resource. The default is 0. See also Resource Sharing.
|
| StreamingFactor | Number of parallel data paths, or vectors, that are time multiplexed
to transform into serial, scalar data paths. The default is 0, which
implements fully parallel data paths. See also Streaming.
|
If this block is not the DUT, the block property settings in the Target
Specification tab are ignored. In the HDL Workflow Advisor, if you use the
IP Core Generation workflow, these target specification block
property values are saved with the model. If you specify these target specification block
property values using hdlset_param, when you open HDL Workflow Advisor,
the fields are populated with the corresponding values.
| Target Specification |
|---|
| AdditionalTargetInterfaces |
Additional target interfaces, specified as a character vector.
To save this block property on the model, in the Set Target
Interface task of the IP Core
Generation workflow, corresponding to the DUT ports that
you want to add more interfaces, select Add
more.... You can then add more interfaces in the Add New
Target Interfaces dialog box. Specify the type of interface, number of
additional interfaces, and a unique name for each additional
interface.
Values: '' (default) | cell array of character
vectors
Example:
'{{'AXI4-Stream','InterfaceID','AXI4-Stream1'}}'
|
| ProcessorFPGASynchronization | Processor/FPGA synchronization mode, specified as a character
vector. To save this block property on the model, specify the Processor/FPGA
Synchronization in the Set Target
Interface task of the IP Core Generation
workflow. Values: Free running (default) | Coprocessing
- blocking Example: 'Free running' |
| TestPointMapping | To save this block property on the model, specify the mapping of test
point ports to target platform interfaces in the Set Target
Interface task of the IP Core Generation
workflow. Values: '' (default) | cell array of character
vectors Example: '{{'TestPoint','AXI4-Lite','x"108"'}}' |
| TunableParameterMapping | To save this block property on the model, specify the mapping of tunable
parameter ports to target platform interfaces in the Set Target
Interface task of the IP Core Generation
workflow. Values: '' (default) | cell array of character
vectors Example: '{{'myParam','AXI4-Lite','x"108"'}}' |
| AXI4RegisterReadback | To save this block property on the model, specify whether you want to enable readback on AXI4
subordinate write registers in the Generate RTL Code and IP
Core task of the IP Core Generation
workflow. To learn more, see Model Design for AXI4 Slave Interface Generation. Values: 'off' (default) |
'on' |
| AXI4SlaveIDWidth |
To save this block property on the model, specify the number of AXI
manager interfaces that you want to connect the DUT IP core to by using
the AXI4 Slave ID Width
setting in the Generate RTL Code and IP Core task
of the IP Core Generation workflow. To learn more,
see Define Multiple AXI Master Interfaces in Reference Designs to Access DUT AXI4 Slave Interface.
Values: 'off' (default) |
'on'
|
| RegisterInterfaceReadPipeline |
To save this block property on the model, Specify the number of
pipeline stages to insert in the read address decoder path by using the
Register interface read
pipeline setting in the Generate RTL Code and
IP Core task of the IP Core
Generation workflow. To learn more, see Model Design for AXI4 Slave Interface Generation.
Values: 0 (default) |
|
| GenerateDefaultAXI4Slave | To save this block property on the model, specify whether you want to disable generation of
default AXI4 subordinate interfaces in the Generate RTL Code
and IP Core task of the IP Core
Generation workflow. Values: 'on' (default) |
'off' |
| IPCoreAdditionalFiles | Verilog®, SystemVerilog, or VHDL® files for black boxes in your design. Specify the full
path to each file, and separate file names with a semicolon (;). You can set this property in the HDL Workflow Advisor, in the Additional
source files field. Values: '' (default) | character vector Example: 'C:\myprojfiles\led_blinking_file1.vhd;C:\myprojfiles\led_blinking_file2.vhd;' |
| IPCoreName | IP core name, specified as a character vector. You can set this property in the HDL Workflow Advisor, in the IP
core name field. If this property is set to the default
value, the HDL Workflow Advisor constructs the IP core name based
on the name of the DUT. Values: '' (default) | character vector Example: 'my_model_name' |
| IPCoreVersion | IP core version number, specified as a character vector. You can set this property in the HDL Workflow Advisor, in the IP
core version field. If this property is set to the default
value, the HDL Workflow Advisor sets the IP core version. Values: '' (default) | character vector Example: '1.3' |
| IPDataCaptureBufferSize |
FPGA Data Capture buffer size, specified as a character vector. Use
FPGA Data Capture to observe signals in a design when running on an
FPGA.
The buffer size uses values that are 128*2^n, where n is an integer.
By default, the buffer size is 128 (n=0). The maximum value of n is 13,
which means that the maximum value for buffer size is 1048576
(=128*2^13).
Values: '' (default) | character vector
Example: '1.3'
|
RestrictionsIf your DUT is a masked subsystem, you can generate code only if it is at the top
level of the model.
