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Map Bus Data Types to PCIe Interface

When you use bus data types at the DUT interface ports, you can directly map the interface ports to PCIe interfaces.

When you map bus data types, HDL Coder™ assigns a unique address for each data port that you want to map to the PCIe interface. The top-level and sub-level buses do not have a register offset address. The address mapping for separate scalar or vector bus elements is not contiguous.

Model Bus Element

Model a bus element by using a bus creator block or bus element block to create a bus port.

Model a bus element by using a bus creator block.

Different data types connected to a bus creator block with the bus creator block parameters window open

Model a bus element by using bus element blocks:Different data types connected to a bus element block with the bus element block parameters winddow open

For an example that maps bus data type to PCIe Interface, see FPGA Programming and Configuration on Speedgoat Simulink-Programmable I/O Modules.